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1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles
2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
2.5.3. Agilex™ 7 I-Series Devices with F-Tiles
2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
2.5.5. Agilex™ 7 M-Series Devices with HBM2e
2.5.6. Agilex™ 7 M-Series Devices without HBM2e
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8.2.1. Pre-Configuration BSDL Files
Intel provides IEEE 1149.6 BSDL models for Agilex™ 7 devices for pre-configuration boundary-scan testing (BST). IEEE std 1149.6 compliant models are provided with the exception that the SAMPLE instruction which is not supported for all HSSI pins.
Models are density and package specific. You can use the BSDL Model regardless of the device’s speed grade or temperature. Visit the linked BSDL Device Family Collection to access the BSDL Models.