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1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles
2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
2.5.3. Agilex™ 7 I-Series Devices with F-Tiles
2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
2.5.5. Agilex™ 7 M-Series Devices with HBM2e
2.5.6. Agilex™ 7 M-Series Devices without HBM2e
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2.3. Series/Package/Tile Comparison Table
Agilex™ 7 F-Series feature up to four transceiver tiles, I-Series feature up to six transceiver tiles, while the M-Series features four transceiver tiles and up to two HBM2e tiles. A variety of packages are offered. Dimensions shown are nominal.
Series | Package Code | Size (mm x mm) | Pin/Ball Count | Tile x Quantity |
---|---|---|---|---|
F-Series | R24D | 45 x 42 | 2340 | F x1 |
R16A | 37.5 x 34 | 1546 | F x2 | |
R24C | 45 x 42 | 2340 | F x2 | |
R31C | 56 x 45 | 3184 | F x4 | |
R24B | 55 x 42.5 | 2486 | P x1, E x1 | |
R25A | 52.5 x 40.5 | 2581 | P x2, E x1 | |
I-Series | R18A | 42.5 x 42.5 | 1805 | R x1, F x1 |
R29A/D | 56 x 45 | 2957 | R x3, F x1 | |
R31A | 56 x 45 | 3184 | R x1, F x3 | |
R31B | 56 x 45 | 3184 | F x4 | |
R39A | 56 x 56 | 3984 | F x6 | |
M-Series | R31B | 56 x 45 | 3184 | F x4 |
R47A | 56 x 66 | 4700 | F x3, R x1, HBM2e x2 | |
R47B | 56 x 66 | 4700 | F x4, HBM2e x2 |