Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

ID 814028
Date 6/07/2024
Public
Document Table of Contents

5.3.1.3. Hard Processor System (HPS) I/O

The HPS banks support 1.8 V singled-ended non-voltage referenced I/O standard signaling. Note that the HPS I/O support a wide variety of functions within the HPS block. Refer to the HPS Pin MUX settings for options in Hard Processor System (HPS) Pin Information for Agilex™ 7 SoC Devices - XLS Format (Alt. Format PDF).