Visible to Intel only — GUID: uso1708315374238
Ixiasoft
Visible to Intel only — GUID: uso1708315374238
Ixiasoft
6.10.2. Schematic Design
General comments on schematic design for a complex FPGA application would include System and Block level diagrams, functional block partitioning for schematic readability and ease of use. It is recommended to include a notation of the Quartus Pin-File used and its revision to denote the synchronization between the FPGA IP Design in Quartus, and the board schematic. Other common call outs to include are special placement or layout instructions. Typically, the schematic partitions are:
- FPGA
- FPGA Block Diagrams
- High-Speed Serial Interfaces/Transceivers
- EMIF
- Clocks
- Control Buses
- Special Blocks (HPS, DAC/ADC, and others)
- GPIO
- Power Management:
- Power Tree and SmartVID
- Decoupling Capacitors
- Board Management Controller (BMC)/Power Sequence Logic
- Configuration and Power On Reset
- Connectors (Internal and External)
- Rest of the system
- Schematic Revision History
System/Supply monitoring may also be desired. This may include voltage rail, current magnitude, and temperature monitoring. Additional status monitors such as CONF_DONE, INIT_DONE, nSTATUS, and other application-specific signals such as PLL Lock signals may be useful to monitor in the bring-up stage. They can be DNI’ed (Do Not Install) in the production stage if they are not exposed to the end user of the system.
In parallel to Schematic Design, the FPGA Designer would be completing the FPGA IP design and reviewing and checking the I/O Ring, EMIF, and other selected pin locations as required to ensure Quartus, and the Board design are in alignment and will compile.