Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

ID 814028
Date 6/07/2024
Public
Document Table of Contents

5.3.2. Bank Locations

Banks are located on the top and bottom of the device while tiles are located to the sides. The Quartus® Prime Pin Planner is also useful to see color coded bank groupings.

Note: The Pin Planner does not take pin pitch into account and is conceptual only and is not to scale. Due to pin density the image may be distorted, therefore take note of Pin 1 location for correct orientation.