Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

ID 814028
Date 6/07/2024
Public
Document Table of Contents

2.5. Series Package Options Versus Tiles—Support I/O Counts

The tables in this section describe the series package options versus tiles supported for the following series/tiles matrix. I/O type and counts are provided. The PCB footprint compatibility is shown in the respective package columns. Compatibility checks are required.

  • Agilex™ 7 F-Series Devices with F-Tiles
  • Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
  • Agilex™ 7 I-Series Devices with F-Tiles
  • Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
  • Agilex™ 7 M-Series Devices with HBM2e
  • Agilex™ 7 M-Series Devices without HBM2e
Note: One F-Tile contains up to twenty transceivers (16x FGT and 4x FHT). Here, FGT refers to F-Tile General-purpose Transceiver, and FHT refers to F-Tile High-speed Transceiver.
Refer to the Agilex™ 7 FPGAs and SoCs Device Overview for a detailed explanation of the FPGA Transceivers and Heterogeneous 3D Stacked HBM2e DRAM Memory.