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1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles
2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
2.5.3. Agilex™ 7 I-Series Devices with F-Tiles
2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
2.5.5. Agilex™ 7 M-Series Devices with HBM2e
2.5.6. Agilex™ 7 M-Series Devices without HBM2e
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2.5. Series Package Options Versus Tiles—Support I/O Counts
The tables in this section describe the series package options versus tiles supported for the following series/tiles matrix. I/O type and counts are provided. The PCB footprint compatibility is shown in the respective package columns. Compatibility checks are required.
- Agilex™ 7 F-Series Devices with F-Tiles
- Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
- Agilex™ 7 I-Series Devices with F-Tiles
- Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
- Agilex™ 7 M-Series Devices with HBM2e
- Agilex™ 7 M-Series Devices without HBM2e
Note: One F-Tile contains up to twenty transceivers (16x FGT and 4x FHT). Here, FGT refers to F-Tile General-purpose Transceiver, and FHT refers to F-Tile High-speed Transceiver.
Refer to the Agilex™ 7 FPGAs and SoCs Device Overview for a detailed explanation of the FPGA Transceivers and Heterogeneous 3D Stacked HBM2e DRAM Memory.