Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

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ID 814028
Date 6/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Product Family Plan 3. Package Information 4. Thermal Design Considerations 5. Pin Connection Guidelines and Pinouts 6. Printed Circuit Board (PCB) Design 7. Signal Integrity Simulations 8. Validation 9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
1. Introduction x
1.1. Status Definitions 1.2. Notifications 1.3. Secure Asset Access—Developer Zone Premium (DZP)
2. Product Family Plan x
2.1. Product Table Information 2.2. Part Number Decoder 2.3. Series/Package/Tile Comparison Table 2.4. Migration within a Package 2.5. Series Package Options Versus Tiles—Support I/O Counts 2.6. Package Comparison Tables
2.5. Series Package Options Versus Tiles—Support I/O Counts x
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles 2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles 2.5.3. Agilex™ 7 I-Series Devices with F-Tiles 2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles 2.5.5. Agilex™ 7 M-Series Devices with HBM2e 2.5.6. Agilex™ 7 M-Series Devices without HBM2e
3. Package Information x
3.1. Ball Grid Array (BGA) Package
3.1. Ball Grid Array (BGA) Package x
3.1.1. Package Mechanical Drawings 3.1.2. Package Ball Coordinates 3.1.3. Package PCB Footprints 3.1.4. Land Pattern PCB Design Recommendations (MAS)
4. Thermal Design Considerations x
4.1. Power Estimation and Analysis Tools 4.2. Compact Thermal Models (CTM) 4.3. Heat Sink 4.4. Remote Temperature Sensing using Temperature Sensing Diodes (TSDs)
4.1. Power Estimation and Analysis Tools x
4.1.1. Intel® FPGA Power and Thermal Calculator (PTC) 4.1.2. Quartus® Prime Power Analyzer (QPA)
4.3. Heat Sink x
4.3.1. Heat Sink Rework
5. Pin Connection Guidelines and Pinouts x
5.1. Pin Connection Guidelines 5.2. Pinout Introduction 5.3. I/O Banks 5.4. Transceivers 5.5. Validating Pins
5.2. Pinout Introduction x
5.2.1. F-Series Pinouts 5.2.2. I-Series Pinouts 5.2.3. M-Series Pinouts 5.2.4. Hard Processor System (HPS) Pin Information 5.2.5. External Memory Interface (EMIF) Pin Information
5.3. I/O Banks x
5.3.1. Types of Banks 5.3.2. Bank Locations 5.3.3. Selecting Bank Usage
5.3.1. Types of Banks x
5.3.1.1. General-purpose I/O (GPIO) 5.3.1.2. Secure Device Manager (SDM) I/O 5.3.1.3. Hard Processor System (HPS) I/O
5.3.3. Selecting Bank Usage x
5.3.3.1. Agilex™ 7 M-Series FPGA I/O Placement
6. Printed Circuit Board (PCB) Design x
6.1. Schematic Symbols 6.2. Power Supply 6.3. External Memory 6.4. Transceivers 6.5. SoC FPGA Hard Processor Systems (HPS) 6.6. JTAG Interface 6.7. FPGA Configuration 6.8. Development Kit Examples 6.9. Schematic Review Worksheet 6.10. Step-by-Step Generic PCB Design Flow
6.4. Transceivers x
6.4.1. High-Speed Serial Interface Signal Integrity Design Guidelines 6.4.2. Tiles
6.4.2. Tiles x
6.4.2.1. F-Tile Transceivers 6.4.2.2. E-Tile Transceivers 6.4.2.3. P-Tile Transceivers 6.4.2.4. R-Tile Transceivers
6.10. Step-by-Step Generic PCB Design Flow x
6.10.1. Getting Ready 6.10.2. Schematic Design 6.10.3. Board Layout 6.10.4. Checks
7. Signal Integrity Simulations x
7.1. Intel Advanced Link Analyzer 7.2. Signal Integrity Analysis with Third-Party Tools 7.3. IBIS Models 7.4. Transceiver IBIS-AMI Models 7.5. Net Length Reports
8. Validation x
8.1. Validation and Debug Tools 8.2. Boundary-Scan Description Language (BSDL) Models
8.1. Validation and Debug Tools x
8.1.1. Transceiver Toolkit 8.1.2. EMIF Toolkit and Debug Tools 8.1.3. System Console 8.1.4. Signal Tap 8.1.5. Programmer’s Configuration Debugger Tool
8.2. Boundary-Scan Description Language (BSDL) Models x
8.2.1. Pre-Configuration BSDL Files 8.2.2. Post-Configuration BSDL Generator
1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide

2.4. Migration within a Package

Vertical migration starts with printed circuit board (PCB) land pattern compatibility. This allows for different-density devices within a package type to be supported by the hardware with certain considerations. The I/O resources may vary by the device density. Utilize the I/O that is common to "all" targeted densities first for maximum device flexibility.

In general, there are usually a pair of devices that are similar and mainly differ in logic density with direct compatibility. Additional device densities may be offered in that same package footprint (PCB land pattern) but may have different core resources, supported functions or other differences.

There may be other mechanical considerations to be aware of and to review. The Top Lid heat sink mounting area of the package may vary as can the overall height (Z), for example, R25A. Ensure compatibility with the thermal design of the system and its manufacturing flow.

Functional capability differences may also exist. This may include I/O, EMIF, temperature sensors, bit stream size, supported device features, power requirements, and the required decoupling capacitors.

In general, you must determine the largest density for the application and base the board design on those requirements. It is easier to scale down the power supply system than up for example.

Before fabricating the printed circuit board, you must run compilation checks in the Quartus® Prime Pro Edition design software to validate both pin and IP functional compatibility. Ensure that the compilation passes without any fitter error.

Refer to the Pin Migration Window to verify if pin assignments are compatible to different density devices in the same device package in the Quartus® Prime Pro Edition design software.

There are a number of special cases that are conditional migration examples and additional guidance from Intel is recommended to accommodate these cases. The following table lists the conditional migration examples and are flagged in the other tables with a footnote.

Table 3.  Conditional Migration Examples
Conditional Migration Differences Package(s)
AGF 019/023 R25A AGF 022/027 R25A Features, I/O Placement, Package Height R25A
AGI 022/027 R29A AGI 041 R29D Features, I/O Placement R29A / R29D
AGI 027 R31B AGI 041 R31B Features, I/O Placement R31B
AGI 022/027 R31B AGM 032/039 R31B Features (I-Series to M-Series) R31B
AGF 019/023 R31C AGI 019/023 R31B FHT XCVR (F-Series to I-Series) R31C / R31B
AGF 022/027 R31C AGI 022/027 R31B FHT XCVR (F-Series to I-Series) R31C / R31B

The tables in Series Package Options vs Tiles – Support I/O Counts section indicate the vertical migration supported by the common package land patterns.

For additional migration information, refer to the package information section in the respective Agilex™ 7 product tables.

You can also refer to the Device Migration section in the AN 886: Agilex™ 7 Device Design Guidelines for a discussion on the vertical, horizontal, and conditional migration between devices.

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