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1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles
2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
2.5.3. Agilex™ 7 I-Series Devices with F-Tiles
2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
2.5.5. Agilex™ 7 M-Series Devices with HBM2e
2.5.6. Agilex™ 7 M-Series Devices without HBM2e
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3.1. Ball Grid Array (BGA) Package
Agilex™ 7 FPGAs and SoC FPGAs are offered in a ball grid array (BGA) packages with a copper integrated heat spreader (IHS). The BGA package can be rectangle or square, and may contain several types of dies, such as core, tile, and HBM2e.
The package code includes a BGA designator, an approximation of the ball count magnitude, and variant. For example, the R24C package code digits stand for:
- R—Rectangular Flip-Chip Ball Grid Array (FCBGA) package
- 24—represents ball count in 2-digit format. For example, 24 = 2340.
- C—variant (which is for a different pinout and or different package)