Visible to Intel only — GUID: hns1708313639525
Ixiasoft
1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles
2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
2.5.3. Agilex™ 7 I-Series Devices with F-Tiles
2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
2.5.5. Agilex™ 7 M-Series Devices with HBM2e
2.5.6. Agilex™ 7 M-Series Devices without HBM2e
Visible to Intel only — GUID: hns1708313639525
Ixiasoft
5.1. Pin Connection Guidelines
The Pin Connection Guidelines describes the available device pins and provides connection guidelines for each pin. Core pins, tile pins, and Hard Processor System (HPS) pins are listed and defined in table format, with columns consisting of Pin Name, Pin Function, Pin Description, and Connection Recommendations. Power supply sharing examples are also provided. These documents are available in HTML and PDF formats.
For complete information, refer to the Pin Connection Guidelines.