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1. Introduction
2. Product Family Plan
3. Package Information
4. Thermal Design Considerations
5. Pin Connection Guidelines and Pinouts
6. Printed Circuit Board (PCB) Design
7. Signal Integrity Simulations
8. Validation
9. Document Revision History for the Agilex™ 7 FPGAs and SoC FPGAs Package, Pinout, and PCB Design User Guide
2.5.1. Agilex™ 7 F-Series Devices with F-Tiles
2.5.2. Agilex™ 7 F-Series Devices with E-Tile and P-Tiles
2.5.3. Agilex™ 7 I-Series Devices with F-Tiles
2.5.4. Agilex™ 7 I-Series Devices with F-Tiles and R-Tiles
2.5.5. Agilex™ 7 M-Series Devices with HBM2e
2.5.6. Agilex™ 7 M-Series Devices without HBM2e
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8.1.1. Transceiver Toolkit
Transceiver Toolkit uses system console technology to help FPGA and board designers validate transceiver link signal integrity real-time in a system and improve board bring-up time. Test for bit-error rate (BER) while simultaneously running multiple links at your target data rate to validate your board design with Transceiver Toolkit. Tune transceiver analog settings for optimal link performance while using different test metrics to quantify results. Simultaneously, test multiple devices across one or more boards using link tests in the Transceiver Toolkit GUI. Support for Agilex™ 7 FPGAs includes adaptive equalization (AEQ) and decision feedback equalization (DFE) for signal transmission robustness. An accessible JTAG port connection is required.