Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

Transmitter Specifications

Table 71.  Transmitter Electrical Specifications For specification status, see the Data Sheet Status table
Parameter Symbol Description Condition Min Typical Max Unit
On-chip termination Transmitter differential on-chip termination resistors 80 90 120
Transmitter output eye specifications VTX-DIFF-PKPK Back-porch transmit amplitude 300  1,050 mV
VTX-DEEMP_STEP Transmitter tap resolution 2 %
DTX-PRE_TAP_2 Pre-cursor tap 2 de-emphasis 0 2.5 dB
DTX-PRE_TAP_1 Pre-cursor tap 1 de-emphasis 0 4.5 dB
DTX-POST_TAP_1 Post-cursor tap 1 de-emphasis 0 6.5 dB
TTX-SLEW Rise/fall time at 20%–80% 10 20 ps
TTX-DJ Transmitter deterministic jitter at 25 Gbps 0.15 UIpkpk
TTX-RJ Transmitter total peak-peak random jitter129 At BER of 10-12 0.15 UIpkpk
TTX-TJ Transmitter total peak-peak jitter (TTX-TJ = TTX-DDJ + TTX-PJ + TTX-RJ)129 130 At BER of 10-12 0.28 UIpkpk
Transmitter DC impedance ZTX-DIFF-DC Transmitter output differential DC impedance with OCT 90 Ω mode while configured131 80 90 120
ZTX-CM-DC Transmitter output common-mode DC impedance 20 22.5 30
Transmitter return loss ZRL-DIFF-DC Transmitter differential DC return loss –12 dB
ZRL-DIFF-NYQ Transmitter differential return loss at Nyquist frequency (FBAUD/2) –6 dB
ZRL-CMN Transmitter common-mode return loss below 10 GHz –6 dB
Electrical idle VTX-IDLE Electrical idle output voltage PCIe*/SATA/SAS/USB 20 mV
VCM-DELTA-SQUELCH Maximum common-mode step entering/exiting squelch mode 100 mV
TTX-IDLE-LATENCY Latency entering/exiting electrical idle 8 µs
Receiver detect VTX-RCV-DETECT Receiver detect voltage change allowed during receiver detection PCIe*/SATA/SAS/USB 600 mV
Lane-to-lane output skew Lane-to-lane output skew 4 < Lane count ≤ 8 2 UI + 250 ps ps
Lane count ≤ 4 2 UI + 166 ps ps
129 Assume a 1st order high-pass jitter measurement filter with a cutoff of FBAUD/FGPLL = NGPLL, where NGPLL is the ratio of the 3 dB cutoff frequency to the data rate, with typical value of 1,667.
130 The maximum TJ value is slightly less than the sum of DDJ + PJ + RJ to take into consideration of the worst case probability, where both deterministic and random jitter component might present at the same time.
131 TX pins are driven to 0 V before configuration.