Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

Transmitter Specifications

Table 71.  Transmitter Electrical Specifications For specification status, see the Data Sheet Status table
Parameter Symbol Description Condition Min Typical Max Unit
On-chip termination — Transmitter differential on-chip termination resistors — 80 90 120 Ω
Transmitter output eye specifications VTX-DIFF-PKPK Back-porch transmit amplitude — 300  — 1,050 mV
VTX-DEEMP_STEP Transmitter tap resolution — — — 2 %
DTX-PRE_TAP_2 Pre-cursor tap 2 de-emphasis — 0 — 2.5 dB
DTX-PRE_TAP_1 Pre-cursor tap 1 de-emphasis — 0 — 4.5 dB
DTX-POST_TAP_1 Post-cursor tap 1 de-emphasis — 0 — 6.5 dB
TTX-SLEW Rise/fall time at 20%–80% — 10 — 20 ps
TTX-DJ Transmitter deterministic jitter at 25 Gbps — — — 0.15 UIpkpk
TTX-RJ Transmitter total peak-peak random jitter129 At BER of 10-12 — — 0.15 UIpkpk
TTX-TJ Transmitter total peak-peak jitter (TTX-TJ = TTX-DDJ + TTX-PJ + TTX-RJ)129 130 At BER of 10-12 — — 0.28 UIpkpk
Transmitter DC impedance ZTX-DIFF-DC Transmitter output differential DC impedance with OCT 90 Ω mode while configured131 — 80 90 120 Ω
ZTX-CM-DC Transmitter output common-mode DC impedance — 20 22.5 30 Ω
Transmitter return loss ZRL-DIFF-DC Transmitter differential DC return loss — — — –12 dB
ZRL-DIFF-NYQ Transmitter differential return loss at Nyquist frequency (FBAUD/2) — — — –6 dB
ZRL-CMN Transmitter common-mode return loss below 10 GHz — — — –6 dB
Electrical idle VTX-IDLE Electrical idle output voltage PCIe*/SATA/SAS/USB — — 20 mV
VCM-DELTA-SQUELCH Maximum common-mode step entering/exiting squelch mode — — 100 mV
TTX-IDLE-LATENCY Latency entering/exiting electrical idle — — 8 µs
Receiver detect VTX-RCV-DETECT Receiver detect voltage change allowed during receiver detection PCIe*/SATA/SAS/USB — — 600 mV
Lane-to-lane output skew — Lane-to-lane output skew 4 < Lane count ≤ 8 — — 2 UI + 250 ps ps
Lane count ≤ 4 — — 2 UI + 166 ps ps
129 Assume a 1st order high-pass jitter measurement filter with a cutoff of FBAUD/FGPLL = NGPLL, where NGPLL is the ratio of the 3 dB cutoff frequency to the data rate, with typical value of 1,667.
130 The maximum TJ value is slightly less than the sum of DDJ + PJ + RJ to take into consideration of the worst case probability, where both deterministic and random jitter component might present at the same time.
131 TX pins are driven to 0 V before configuration.
Level Two Title