Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 8/05/2024
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Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

Absolute Maximum Ratings

This section defines the maximum operating conditions. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.

CAUTION:
Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Table 3.  D-Series FPGAs Absolute Maximum Ratings For specification status, see the Data Sheet Status table
Symbol Description Condition Minimum Maximum Unit
VCC Core voltage supply — –0.5 1.21 V
VCCP Periphery supply voltage for the I/O banks — –0.5 1.21 V
VCCH_SDM SDM block AIB I/O supply voltage sense — –0.5 1.332 V
VCCPT Power supply for I/O, DTS, SDM, and system PLL — –0.5 2.08 V
VCCRCORE Power supply for programmable power technology — –0.5 1.64 V
VCCBAT Battery back-up power supply (for design security volatile key register) — –0.5 2.08 V
VCCIO_PIO_SDM SDM block I/O supply voltage sense of bank 3A 1.2 V –0.5 1.6 V
VCC_IO_SDM I/O digital supply voltage sense in SDM block — –0.5 1.21 V
VCCIO_SDM SDM block configuration pins power supply — –0.5 2.08 V
VCCL_ADC_SDM Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices — –0.5 1.21 V
VCCL_SDM SDM digital power supply — –0.5 1.07 V
VCC_HSSI_[L1, R4] Transceiver, system PLL, and hard IP digital power supply — –0.5 1.07 V
VCCPLLDIG_SDM SDM block PLL digital power supply — –0.5 1.07 V
VCCPLL_SDM SDM block PLL analog power supply — –0.5 2.08 V
VCCFUSEWR_SDM Fuse block writing power supply — –0.5 2.08 V
VCCADC ADC voltage sensor power supply — –0.5 2.08 V
VCCL_HPS HPS DSU voltage and periphery circuitry power supply — –0.5 1.21 V
VCCL_HPS_CORE0_CORE1 HPS A55 cores power rail — –0.5 1.21 V
VCCL_HPS_CORE2 HPS A76 core power rail — –0.5 1.21 V
VCCL_HPS_CORE3 HPS A76 core power rail — –0.5 1.21 V
VCCPLLDIG1_HPS HPS PLL1 digital power supply — –0.5 1.21 V
VCCPLLDIG2_HPS HPS PLL2 digital power supply — –0.5 1.21 V
VCCPLL1_HPS HPS PLL1 analog power supply — –0.5 2.08 V
VCCPLL2_HPS HPS PLL2 analog power supply — –0.5 2.08 V
VCCIO_HPS HPS I/O buffers power supply — –0.5 2.08 V
VCCEHT_GTS[L1, R4][A, B, C, D] Transceiver PMA, TX PLL, transceiver reference clock, and global reference clock high-voltage analog power supply — –0.5 2.08 V
VCCERT_GTS[L1, R4][A, B, C, D] Transceiver PMA, transceiver reference clock, and global reference clock low-voltage analog power supply — –0.5 1.34 V
VCCIO_PIO HSIO bank power supply VCCIO_PIO = 1.0 V –0.5 1.365 V
VCCIO_PIO = 1.05 V –0.5 1.43 V
VCCIO_PIO = 1.1 V –0.5 1.5 V
VCCIO_PIO = 1.2 V –0.5 1.64 V
VCCIO_PIO = 1.3 V –0.5 1.74 V
VCCIO_HVIO HVIO bank power supply VCCIO_HVIO = 3.3 V –0.5 3.74 V
VCCIO_HVIO = 2.5 V –0.5 2.83 V
VCCIO_HVIO = 1.8 V –0.5 2.04 V
VCCPT_HVIO Supply voltage for 1.8 V I/O — –0.5 2.04 V
VI DC input voltage VCCIO_PIO = 1.0 V1 2 –0.3 VCCIO_PIO(MAX) + 0.25 V
VCCIO_PIO = 1.05 V1 2 –0.3 VCCIO_PIO(MAX) + 0.25 V
VCCIO_PIO = 1.1 V1 2 –0.3 VCCIO_PIO(MAX) + 0.25 V
VCCIO_PIO = 1.2 V1 2 –0.3 VCCIO_PIO(MAX) + 0.25 V
VCCIO_PIO = 1.3 V1 2 –0.3 VCCIO_PIO(MAX) + 0.25 V
VCCIO_SDM = 1.8 V –0.3 VCCIO_SDM(MAX) + 0.3 V
VCCIO_HPS = 1.8 V –0.3 VCCIO_HPS(MAX) + 0.3 V
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V –0.3 VCCIO_HVIO(MAX) + 0.3 V
IOUT 3 4 DC output current per pin VCCIO_PIO = 1.0 V, 1.05 V, 1.1 V, 1.2 V, 1.3 V 5 6 –7.5 7.5 mA
VCCIO_SDM, VCCIO_HPS = 1.8 V 7 –20 20 mA
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 12 mA8 9 –8 8 mA
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 9 mA8 9 –6 6 mA
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 6 mA8 9 –4 4 mA
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 3 mA8 9 –2 2 mA
TJ 10 Absolute junction temperature — –40 125 °C
TSTG Storage temperature — –55 150 °C
Table 4.  E-Series FPGAs Absolute Maximum Ratings For specification status, see the Data Sheet Status table
Symbol Description Condition Minimum Maximum Unit
VCC Core voltage supply SmartVID: –1V, –2V, –2E, –3V –0.5 1.21 V
Fixed voltage: –4S –0.5 1.07 V
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –6S, –6X –0.5 1.004 V
VCCP Periphery supply voltage for the I/O banks SmartVID: –1V, –2V, –2E, –3V –0.5 1.21 V
Fixed voltage: –4S –0.5 1.07 V
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –6S, –6X –0.5 1.004 V
VCCH_SDM SDM block AIB I/O supply voltage sense SmartVID: –1V, –2V, –2E, –3V –0.5 1.07 V
Without Transceiver: –4S –0.5 1.07 V
Without Transceiver: –5S, –0.5 1.043 V
Without Transceiver: –6S, –6X –0.5 1.004 V
With Transceiver –0.5 1.332 V
VCCPT Power supply for I/O, DTS, SDM, and system PLL — –0.5 2.08 V
VCCRCORE Power supply for programmable power technology — –0.5 1.64 V
VCCBAT Battery back-up power supply (for design security volatile key register) — –0.5 2.08 V
VCCIO_PIO_SDM SDM block I/O supply voltage sense of bank 3A 1.2 V –0.5 1.6 V
VCC_IO_SDM I/O digital supply voltage sense in SDM block SmartVID: –1V, –2V, –2E, –3V –0.5 1.21 V
Fixed voltage: –4S –0.5 1.07 V
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –6S, –6X –0.5 1.004 V
VCCIO_SDM SDM block configuration pins power supply — –0.5 2.08 V
VCCL_ADC_SDM Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices SmartVID: –1V, –2V, –2E, –3V –0.5 1.21 V
Fixed voltage: –4S –0.5 1.07 V
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –5S, –6S, –6X –0.5 1.004 V
VCCL_SDM SDM digital power supply SmartVID: –1V, –2V, –2E, –3V –0.5 1.07 V
Fixed voltage: –4S –0.5 1.07 V
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –5S, –6S, –6X –0.5 1.004 V
VCC_HSSI_[L1, R4] Transceiver, system PLL, and hard IP digital power supply SmartVID: –1V, –2V, –2E, –3V –0.5 1.07 V
Fixed voltage: –4S –0.5 1.07  
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –6S, –6X –0.5 1.004 V
VCCPLLDIG_SDM SDM block PLL digital power supply SmartVID: –1V, –2V, –2E, –3V –0.5 1.07 V
Fixed voltage: –4S –0.5 1.07 V
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –6S, –6X –0.5 1.004 V
VCCPLL_SDM SDM block PLL analog power supply — –0.5 2.08 V
VCCFUSEWR_SDM Fuse block writing power supply — –0.5 2.08 V
VCCADC ADC voltage sensor power supply — –0.5 2.08 V
VCCL_HPS HPS DSU voltage and periphery circuitry power supply SmartVID: –1V, –2V, –2E, –3V –0.5 1.21 V
Fixed voltage: –4S –0.5 1.07 V
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –6S, –6X –0.5 1.004 V
VCCL_HPS_CORE0_CORE1 HPS A55 cores power rail SmartVID: –1V, –2V, –2E, –3V –0.5 1.21 V
Fixed voltage: –4S –0.5 1.07 V
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –6S, –6X –0.5 1.004 V
VCCL_HPS_CORE2 HPS A76 core power rail SmartVID: –1V, –2V, –2E, –3V –0.5 1.21 V
Fixed voltage: –4S –0.5 1.07 V
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –6S, –6X –0.5 1.004 V
VCCL_HPS_CORE3 HPS A76 core power rail SmartVID: –1V, –2V, –2E, –3V –0.5 1.21 V
Fixed voltage: –4S –0.5 1.07 V
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –6S, –6X –0.5 1.004 V
VCCPLLDIG1_HPS HPS PLL1 digital power supply SmartVID: –1V, –2V, –2E, –3V –0.5 1.21 V
Fixed voltage: –4S –0.5 1.07 V
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –6S, –6X –0.5 1.004 V
VCCPLLDIG2_HPS HPS PLL2 digital power supply SmartVID: –1V, –2V, –2E, –3V –0.5 1.21 V
Fixed voltage: –4S –0.5 1.07 V
Fixed voltage: –5S –0.5 1.043 V
Fixed voltage: –6S, –6X –0.5 1.004 V
VCCPLL1_HPS HPS PLL1 analog power supply — –0.5 2.08 V
VCCPLL2_HPS HPS PLL2 analog power supply — –0.5 2.08 V
VCCIO_HPS HPS I/O buffers power supply — –0.5 2.08 V
VCCEHT_GTS[L1, R4][A, B, C] Transceiver PMA, TX PLL, transceiver reference clock, and global reference clock high-voltage analog power supply — –0.5 2.08 V
VCCERT_GTS[L1, R4][A, B, C] Transceiver PMA, transceiver reference clock, and global reference clock low-voltage analog power supply — –0.5 1.34 V
VCCIO_PIO HSIO bank power supply VCCIO_PIO = 1.0 V –0.5 1.365 V
VCCIO_PIO = 1.05 V –0.5 1.43 V
VCCIO_PIO = 1.1 V –0.5 1.5 V
VCCIO_PIO = 1.2 V –0.5 1.64 V
VCCIO_PIO = 1.3 V –0.5 1.74 V
VCCIO_HVIO HVIO bank power supply VCCIO_HVIO = 3.3 V –0.5 3.74 V
VCCIO_HVIO = 2.5 V –0.5 2.83 V
VCCIO_HVIO = 1.8 V –0.5 2.04 V
VCCPT_HVIO Supply voltage for 1.8 V I/O — –0.5 2.04 V
VI DC input voltage VCCIO_PIO = 1.0 V11 12 –0.3 VCCIO_PIO(MAX) + 0.25 V
VCCIO_PIO = 1.05 V11 12 –0.3 VCCIO_PIO(MAX) + 0.25 V
VCCIO_PIO = 1.1 V11 12 –0.3 VCCIO_PIO(MAX) + 0.25 V
VCCIO_PIO = 1.2 V11 12 –0.3 VCCIO_PIO(MAX) + 0.25 V
VCCIO_PIO = 1.3 V11 12 –0.3 VCCIO_PIO(MAX) + 0.25 V
VCCIO_SDM = 1.8 V –0.3 VCCIO_SDM(MAX) + 0.3 V
VCCIO_HPS = 1.8 V –0.3 VCCIO_HPS(MAX) + 0.3 V
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V –0.3 VCCIO_HVIO(MAX) + 0.3 V
IOUT 13 14 DC output current per pin VCCIO_PIO = 1.0 V, 1.05 V, 1.1 V, 1.2 V, 1.3 V 15 16 –7.5 7.5 mA
VCCIO_SDM, VCCIO_HPS = 1.8 V 17 –20 20 mA
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 12 mA18 19 –8 8 mA
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 9 mA18 19 –6 6 mA
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 6 mA18 19 –4 4 mA
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V Current Strength Setting = 3 mA18 19 –2 2 mA
TJ 20 Absolute junction temperature — –40 125 °C
TSTG Storage temperature — –55 150 °C
Related Information
1 Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.
2 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI(DC) for the LVCMOS input can go up to VCCIO_PIO(MAX) + 0.3 V.
3 Total current per I/O bank must not exceed 100 mA.
4 Applies to all I/O standards and settings supported by I/O banks, including single-ended and differential I/Os.
5 The maximum current allowed through any HSIO pin during power-up/power-down conditions is 10 mA. Pin voltage during these conditions should not exceed 1.2 V or the VCCIO_PIO supply rail of the bank where the I/O pin resides in, whichever is the lower voltage. While this device is not turned on, the I/O pin should be tri-stated or not driven with any external voltages.
6 The DC output current per pin may exceed 7.5 mA with a duration limit. For more details, refer to the related information.
7 The maximum current allowed through any HPS/SDM pin when the device is not turned on or during power-up/power-down conditions is 10 mA. Pin voltage during these conditions should not exceed VCCIO_HPS or VCCIO_SDM supply rail of the bank where the I/O pin resides in.
8 The maximum current allowed through any HVIO pin when the device is not turned on or during power-up/power-down conditions is 10 mA. Pin voltage during these conditions should not exceed VCCIO_HVIO supply rail of the bank where the I/O pin resides in.
9 The DC output current per pin may exceed specified values with a duration limit. For more details, refer to General Purpose I/O User Guide.
10 When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device lifetime of 11.4 years.
11 Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.
12 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI(DC) for the LVCMOS input can go up to VCCIO_PIO(MAX) + 0.3 V.
13 Total current per I/O bank must not exceed 100 mA.
14 Applies to all I/O standards and settings supported by I/O banks, including single-ended and differential I/Os.
15 The maximum current allowed through any HSIO pin during power-up/power-down conditions is 10 mA. Pin voltage during these conditions should not exceed 1.2 V or the VCCIO_PIO supply rail of the bank where the I/O pin resides in, whichever is the lower voltage. While this device is not turned on, the I/O pin should be tri-stated or not driven with any external voltages.
16 The DC output current per pin may exceed 7.5 mA with a duration limit. For more details, refer to the related information.
17 The maximum current allowed through any HPS/SDM pin when the device is not turned on or during power-up/power-down conditions is 10 mA. Pin voltage during these conditions should not exceed VCCIO_HPS or VCCIO_SDM supply rail of the bank where the I/O pin resides in.
18 The maximum current allowed through any HVIO pin when the device is not turned on or during power-up/power-down conditions is 10 mA. Pin voltage during these conditions should not exceed VCCIO_HVIO supply rail of the bank where the I/O pin resides in.
19 The DC output current per pin may exceed specified values with a duration limit. For more details, refer to General Purpose I/O User Guide.
20 When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device lifetime of 11.4 years.
Level Two Title