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Ixiasoft
HSIO Single-Ended I/O Standards Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
HSIO Single-Ended LVSTL I/O Standards Specifications
HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications
HSIO Differential POD I/O Standards Specifications
HSIO Differential LVSTL I/O Standards Specifications
HSIO Differential I/O Standards Specifications
MIPI D-PHY I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/eMMC Timing Characteristics
HPS USB 2.0 Timing Characteristics
HPS USB 3.1 Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
SGMII Timing Requirements
HPS I2C Timing Characteristics
HPS I3C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
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Ixiasoft
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk (1000Base-T) | TX_CLK clock period | — | 8 | — | ns |
Tclk (100Base-T) | TX_CLK clock period | — | 40 | — | ns |
Tclk (10Base-T) | TX_CLK clock period | — | 400 | — | ns |
Tdutycycle (1000Base-T) | TX_CLK duty cycle | 45 | 50 | 55 | % |
Tdutycycle (10/100Base-T) | TX_CLK duty cycle | 40 | 50 | 60 | % |
Td 147 148 | TXD/TX_CTL to TX_CLK output skew | –0.5 | — | 0.5 | ns |
Figure 20. RGMII TX Timing Diagram
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk (1000Base-T) | RX_CLK clock period | — | 8 | — | ns |
Tclk (100Base-T) | RX_CLK clock period | — | 40 | — | ns |
Tclk (10Base-T) | RX_CLK clock period | — | 400 | — | ns |
Tdutycycle (1000Base-T) | RX_CLK duty cycle | 45 | 50 | 55 | % |
Tdutycycle (10/100Base-T) | RX_CLK duty cycle | 40 | 50 | 60 | % |
Tsu | RX_D/RX_CTL to RX_CLK setup time | 1 | — | — | ns |
Th 149 | RX_CLK to RX_D/RX_CTL hold time | 1 | — | — | ns |
Figure 21. RGMII RX Timing Diagram
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tclk | MDC clock period | 400 | — | — | ns |
Td | MDC to MDIO output data delay | 10 | — | 300 | ns |
Tsu | Setup time for MDIO data | 10 | — | — | ns |
Th | Hold time for MDIO data | 0 | — | — | ns |
Figure 22. MDIO Timing Diagram
SGMII Timing Requirements
SGMII operating mode is supported through FPGA fabric using SGMII PCS soft IP and LVDS SERDES IP. Refer to the LVDS SERDES Specifications section for timing specifications.
SGMII+ operating mode is supported through FPGA fabric using SGMII+ PCS soft IP and serial transceiver interface. Refer to the Transceiver Performance Specifications section for timing specifications.
147 Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.
148 If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5–2.0 ns with the HPS I/O programmable delay, to meet the PHY's 1 ns data-to-clock skew requirement.
149 If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK by 1.5–2 ns, using the HPS I/O programmable delay.