Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

HPS Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 93.  Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) TX_CLK clock period 8 ns
Tclk (100Base-T) TX_CLK clock period 40 ns
Tclk (10Base-T) TX_CLK clock period 400 ns
Tdutycycle (1000Base-T) TX_CLK duty cycle 45 50 55 %
Tdutycycle (10/100Base-T) TX_CLK duty cycle 40 50 60 %
Td 147 148 TXD/TX_CTL to TX_CLK output skew –0.5 0.5 ns
Figure 20. RGMII TX Timing Diagram
Table 94.  RGMII RX Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) RX_CLK clock period 8 ns
Tclk (100Base-T) RX_CLK clock period 40 ns
Tclk (10Base-T) RX_CLK clock period 400 ns
Tdutycycle (1000Base-T) RX_CLK duty cycle 45 50 55 %
Tdutycycle (10/100Base-T) RX_CLK duty cycle 40 50 60 %
Tsu RX_D/RX_CTL to RX_CLK setup time 1 ns
Th 149 RX_CLK to RX_D/RX_CTL hold time 1 ns
Figure 21. RGMII RX Timing Diagram
Table 95.  Management Data Input/Output (MDIO) Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tclk MDC clock period 400 ns
Td MDC to MDIO output data delay 10 300 ns
Tsu Setup time for MDIO data 10 ns
Th Hold time for MDIO data 0 ns
Figure 22. MDIO Timing Diagram

SGMII Timing Requirements

SGMII operating mode is supported through FPGA fabric using SGMII PCS soft IP and LVDS SERDES IP. Refer to the LVDS SERDES Specifications section for timing specifications.

SGMII+ operating mode is supported through FPGA fabric using SGMII+ PCS soft IP and serial transceiver interface. Refer to the Transceiver Performance Specifications section for timing specifications.

147 Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.
148 If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5–2.0 ns with the HPS I/O programmable delay, to meet the PHY's 1 ns data-to-clock skew requirement.
149 If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK by 1.5–2 ns, using the HPS I/O programmable delay.