Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics SGMII Timing Requirements HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

HPS Ethernet Media Access Controller (EMAC) Timing Characteristics

Table 93.  Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) TX_CLK clock period (125 MHz) — 8 — ns
Tclk (100Base-T) TX_CLK clock period (25 MHz) — 40 — ns
Tclk (10Base-T) TX_CLK clock period (2.5 MHz) — 400 — ns
Tdutycycle (1000Base-T) TX_CLK duty cycle 45 50 55 %
Tdutycycle (10/100Base-T) TX_CLK duty cycle 40 50 60 %
Td 150 151 TXD/TX_CTL to TX_CLK output skew –0.5 — 0.5 ns
Figure 20. RGMII TX Timing Diagram
Table 94.  RGMII RX Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tclk (1000Base-T) RX_CLK clock period (125 MHz) — 8 — ns
Tclk (100Base-T) RX_CLK clock period (25 MHz) — 40 — ns
Tclk (10Base-T) RX_CLK clock period (2.5 MHz) — 400 — ns
Tdutycycle (1000Base-T) RX_CLK duty cycle 45 50 55 %
Tdutycycle (10/100Base-T) RX_CLK duty cycle 40 50 60 %
Tsu RX_D/RX_CTL to RX_CLK setup time 1 — — ns
Th 152 RX_CLK to RX_D/RX_CTL hold time 1 — — ns
Figure 21. RGMII RX Timing Diagram
Table 95.  Management Data Input/Output (MDIO) Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Fclk MDC clock frequency — — 2.5 MHz
Tclk MDC clock period 400 — — ns
Td MDC to MDIO output data delay 10 — 300 ns
Tsu Setup time for MDIO data 10 — — ns
Th Hold time for MDIO data 0 — — ns
Figure 22. MDIO Timing Diagram

SGMII Timing Requirements

SGMII operating mode is supported through FPGA fabric using SGMII PCS soft IP and LVDS SERDES IP. Refer to the LVDS SERDES Specifications section for timing specifications.

SGMII+ operating mode is supported through FPGA fabric using SGMII+ PCS soft IP and serial transceiver interface. Refer to the Transceiver Performance Specifications section for timing specifications.

Related Information
150 Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.
151 If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5–2.0 ns with the HPS I/O programmable delay, to meet the PHY's 1 ns data-to-clock skew requirement.
152 If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK by 1.5–2 ns, using the HPS I/O programmable delay.
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