Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 4/07/2025
Public

Visible to Intel only — GUID: jhi1662081533814

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Avalon® Streaming Configuration Timing

Table 111.   Avalon® Streaming Timing Parameters for ×8 and ×16 Configurations For specification status, see the Data Sheet Status table
Symbol Description Minimum Unit
tACLKH AVST_CLK high time 3.6 ns
tACLKL AVST_CLK low time 3.6 ns
tACLKP AVST_CLK period 8 ns
tADSU 186 AVST_DATA setup time before rising edge of AVST_CLK 2.1 ns
tADH 186 AVST_DATA hold time after rising edge of AVST_CLK 0.1 ns
tAVSU AVST_VALID setup time before rising edge of AVST_CLK 2.1 ns
tAVDH AVST_VALID hold time after rising edge of AVST_CLK 0 ns
Figure 52.  Avalon® Streaming Configuration Timing Diagram
186 Data sampled by the FPGA (sink) at the next rising clock edge.