Visible to Intel only — GUID: dyg1662081513740
Ixiasoft
HSIO Single-Ended I/O Standards Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
HSIO Single-Ended LVSTL I/O Standards Specifications
HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications
HSIO Differential POD I/O Standards Specifications
HSIO Differential LVSTL I/O Standards Specifications
HSIO Differential I/O Standards Specifications
MIPI D-PHY I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/eMMC Timing Characteristics
HPS USB 2.0 Timing Characteristics
HPS USB 3.1 Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS I3C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: dyg1662081513740
Ixiasoft
JTAG Configuration Timing
Symbol | Description | Requirement | Unit | |
---|---|---|---|---|
Minimum | Maximum | |||
tJCP | TCK clock period | 30 | — | ns |
tJCH | TCK clock high time | 14 | — | ns |
tJCL | TCK clock low time | 14 | — | ns |
tJPSU (TDI) 170 | TDI JTAG port setup time | 2 | — | ns |
tJPSU (TMS) 170 | TMS JTAG port setup time | 3 | — | ns |
tJPH 170 | JTAG port hold time | 5 | — | ns |
tJPCO | JTAG port clock to output | — | 7171 | ns |
tJPZX | JTAG port high impedance to valid output | — | 14 | ns |
tJPXZ | JTAG port valid output to high impedance | — | 14 | ns |
Figure 49. JTAG Timing Diagram
170 For boundary-scan testing, the TMS and TDI JTAG ports minimum setup time and hold time are 7 ns.
171 Capacitance loading at 10 pF.