Visible to Intel only — GUID: mta1662081237341
Ixiasoft
HSIO Single-Ended I/O Standards Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
HSIO Single-Ended LVSTL I/O Standards Specifications
HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications
HSIO Differential POD I/O Standards Specifications
HSIO Differential LVSTL I/O Standards Specifications
HSIO Differential I/O Standards Specifications
MIPI D-PHY I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/eMMC Timing Characteristics
HPS USB 2.0 Timing Characteristics
HPS USB 3.1 Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS I3C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: mta1662081237341
Ixiasoft
Receiver Specifications
Parameter | Symbol | Description | Condition | Min | Typical | Max | Unit |
---|---|---|---|---|---|---|---|
On-chip termination | — | Receiver differential on-chip termination resistors | — | 65 | 85 | 102 | Ω |
80 | 100 | 120 | Ω | ||||
Receiver input eye specifications | VRX-DIFF-PKPK | Receiver input differential peak-to-peak voltage132 | — | — | — | 1,200 | mV |
VRX-MAX | Receiver input maximum voltage133 | — | — | — | 1 | V | |
VRX-MIN | Receiver input minimum voltage133 | — | –0.3 | — | — | V | |
VRX-CM-DC | Receiver input DC common-mode voltage134 | When squelch detector is not enabled | 0 | — | 700 | mV | |
When squelch detector is enabled | 200 | — | 300 | mV | |||
TRX-RJ | Receiver input random jitter | At BER of 10-12 | — | — | 0.15 | UIpkpk | |
TRX-PJ | Receiver input periodic jitter (at high frequency135 ) | — | — | — | 0.05 | UIpkpk | |
Insertion loss specification | IINS-LOSS-28Gb/s_BER10-15 | Insertion loss at Nyquist frequency (FBAUD/2)136 | At BER of 10-15 | — | — | –27 | dB |
IINS-LOSS-28Gb/s_BER10-12 | At BER of 10-12 | — | — | –30 | dB | ||
IINS-LOSS-17Gb/s_BER10-12 | Insertion loss at Nyquist frequency (FBAUD/2)136 | At BER of 10-12 | — | — | –30 | dB | |
Receiver return loss | ZRL-DIFF-DC | Receiver differential DC return loss | — | — | — | –12 | dB |
ZRL-DIFF-NYQ | Receiver differential return loss at Nyquist frequency (FBAUD/2) | — | — | — | –6 | dB | |
ZRL-CM | Receiver common-mode return loss below 10 GHz | — | — | — | –6 | dB | |
Receiver DC impedance | RDIFF-DC | Receiver differential DC impedance | 85 Ω on-chip termination | 65 | 85 | 102 | Ω |
100 Ω on-chip termination | 80 | 100 | 120 | Ω | |||
RCM-DC | Receiver common-mode DC impedance | — | 20 | 25 | 30 | Ω | |
Receiver signal detection137 | VIDLE-THRESH | Receiver signal detect input voltage threshold | — | 75 | 120 | 175 | mV |
132 This is supported when the receiver is powered and configured, powered and unconfigured, or unpowered.
133 VRX_MAX and VRX_MIN are before and after configuration.
134 The specified common-mode range is supported when the receiver is powered and configured, powered and unconfigured, or unpowered. This specification is also supported before mode configuration. If squelch detect is used, receiver DC input common-mode voltage should be within 200 mV to 300 mV. Otherwise, use AC coupling capacitors on board.
135 High frequency is defined as frequencies beyond the CDR loop bandwidth (typically FBAUD/1,667).
136 COM compliant package and channel.
137 Receiver signal detection values in this table are applicable to PCIe* and similar standards, such as SATA, where a clock pattern like PCIe* EIEOS 500 MHz clock pattern is used.