Visible to Intel only — GUID: mjm1662081288366
Ixiasoft
HSIO Single-Ended I/O Standards Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
HSIO Single-Ended LVSTL I/O Standards Specifications
HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications
HSIO Differential POD I/O Standards Specifications
HSIO Differential LVSTL I/O Standards Specifications
HSIO Differential I/O Standards Specifications
MIPI D-PHY I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/eMMC Timing Characteristics
HPS USB 2.0 Timing Characteristics
HPS USB 3.1 Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS I3C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: mjm1662081288366
Ixiasoft
HPS USB 2.0 Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tusb_clk | USB_CLK clock period (60 MHz) | — | 16.667 | — | ns |
Td | Clock to USB_STP/USB_DATA[7:0] output delay | 2 | — | 7 | ns |
Tsu | Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] | 4 | — | — | ns |
Th | Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] | 4 | — | — | ns |
Figure 18. USB ULPI Timing Diagram
Note: The USB interface supports single data rate (SDR) timing only.