Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

HPS I3C Timing Characteristics

Table 97.  HPS I3C Timing Requirements When Communicating With I2C Legacy Devices For specification status, see the Data Sheet Status table
Symbol Description Fast Mode Fast Mode Plus Unit
Min Max Min Max
fSCL SCL clock frequency 0 0.4 0 1 MHz
TSCL Serial clock (SCL) clock period — 2.5 — 1 μs
Tclk_jitter I3C clock output jitter — 2 — 2 %
THIGH SCL high period 600 — 260 — ns
TDIG_H THIGH + Tscl_r — THIGH + Tscl_r — ns
TLOW SCL low period 1,300 — 500 — ns
TDIG_L TLOW + Tscl_r — TLOW + Tscl_r — ns
TSU_DAT Setup time for serial data line (SDA) data to SCL 100 — 50 — ns
THD_DAT Hold time for SCL to SDA data — — — — —
TSU_STA Setup time for a repeated start condition 600 — 260 — ns
THD_STA Hold time for a repeated start condition 600 — 260 — ns
TSU_STO Setup time for a stop condition 600 — 260 — ns
TBUF SDA high pulse duration between STOP and START 1.3 — 0.5 — μs
Tscl_r SCL rise time 20 300 — 120 ns
Tscl_f SCL fall time 20 × (VCCIO_HPS / 5.5 V)161 300 20 × (VCCIO_HPS / 5.5 V)161 120 ns
Tsda_r SDA rise time 20 300 — 120 ns
Tsda_f SDA fall time 20 × (VCCIO_HPS / 5.5 V)161 300 20 × (VCCIO_HPS / 5.5 V)161 120 ns
TSPIKE Pulse width of spikes that the spike filter must suppress 0 50 0 50 ns
Table 98.  HPS I3C Open Drain Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Max Unit
THIGH SCL high period — 41 ns
TDIG_H — THIGH + TCF ns
TLOW_OD SCL low period 200 — ns
TLOW_OD_L TLOW_ODmin + TfDA_ODmin — ns
TfDA_OD SDA signal fall time TCF 12 ns
TSU_OD Setup time for serial data line (SDA) data to SCL 3 — ns
TCAS 162 Clock after START Condition 38.4 ns For ENTAS0: 1 μs —
For ENTAS1: 100 μs —
For ENTAS2: 2 ms —
For ENTAS3: 50 ms —
TCBP Clock before STOP Condition TCASmin/2 — s
TMMOverlap Current master to secondary master overlap time during handoff TDIG_OD_Lmin — ns
TAVAL Bus available condition 1 — μs
TIDLE Bus IDLE condition 200 — μs
TMMLock Time internal where new master not driving SDA Low TAVALmin — μs
Table 99.  HPS I3C Push-Pull Timing Requirements for SDR Mode For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
fSCL SCL clock frequency 0.01 12.5 12.9 MHz
TCLK Serial clock (SCL) clock period 100 μs — 77.5 ns —
THIGH SCL clock high period 24 — — ns
TDIG_H 32 — — ns
TLOW SCL clock low period 24 — — ns
TDIG_L 32 — — ns
THIGH_MIXED SCL clock high period for mixed bus163 24 — — ns
TDIG_H_MIXED 32 — 45 ns
TSCO Clock in to data out for slave — — 12 ns
TCR SCL rise time — — 150e6 × 1/fSCL (capped at 60 ns) ns
TCF SCL fall time — — 150e6 × 1/fSCL (capped at 60 ns) ns
THD_PP Hold time for SCL to SDA data (master) TCR + 3 and TCF + 3 — — ns
Hold time for SCL to SDA data (slave) 0 — — ns
TSU_PP SDA signal data setup time 3 — — ns
TCASr Clock after repeated START (Sr) TCASmin — — ns
TCBSr Clock before repeated START (Sr) TCASmin / 2 — — ns
Cb Capacitive load per bus Line (SDA/SCL) — — 50 pF
Figure 24. I3C Legacy Mode Timing Diagram
Figure 25. TDIG_H and TDIG_L
Figure 26. I3C Start Condition Timing Diagram
Figure 27. I3C Stop Condition Timing Diagram
Figure 28. I3C Start Master Out Timing Diagram
Figure 29. I3C Slave Out Timing Diagram
Figure 30. Master SDR Timing Diagram
Related Information
161 Refer to the HPS Power Supply Operating Conditions section for VCCIO_HPS values.
162 Enter Activity State (ENTAS) is a Common Command Code (CCC) supported by all I3C master and slave devices.
163 During I3C communication on a mixed bus, to avoid I2C controllers from interpreting I3C signaling as valid I2C signaling, the TDIG_H period must be constrained.
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