Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

HPS SD/eMMC Timing Characteristics

Table 82.  HPS Secure Digital (SD)/Embedded MultiMediaCard (eMMC) Timing Requirements

Supports SD devices up to V6.1. Supports SDIO devices up to V4.1. Supports SD/eMMC devices up to V5.1.

These timings apply to SD, MMC, and eMMC cards operating at 1.8 V.

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit
Tsdmmc_cclk SD SDMMC_CCLK clock period (Identification mode, 400 kHz) 2,500 — — ns
SD SDMMC_CCLK clock period (SDR12, 25 MHz) 40 — — ns
SD SDMMC_CCLK clock period (SDR25, 50 MHz) 20 — — ns
SD SDMMC_CCLK clock period (SDR50, 100 MHz) 10 — — ns
SD SDMMC_CCLK clock period (SDR104, <200 MHz) 5 — — ns
SD SDMMC_CCLK clock period (DDR50, 50 MHz) 20 — — ns
eMMC SDMMC_CCLK clock period (Legacy, 25 MHz) 40 — — ns
eMMC SDMMC_CCLK clock period (HS50 SDR, 50 MHz) 20 — — ns
eMMC SDMMC_CCLK clock period (HS100 DDR, 100 MHz) 10 — — ns
eMMC SDMMC_CCLK clock period (HS200 SDR, 200 MHz) 5 — — ns
eMMC SDMMC_CCLK clock period (HS400 DDR, 200 MHz) 5 — — ns
Tdutycycle SDMMC_CCLK duty cycle 45 50 55 %
Tsdmmc_cclk_jitter SDMMC_CCLK output jitter — — 2 %
Tsdmmc_clk Internal reference clock before division by 4 (200 MHz) 5 — — ns
None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at 1.8 V at power on.
Note: SD cards power up at 3 V. To support SD, your design must include a level shifter between the SD card and the HPS SD/MMC interface.
Table 83.  SD Input Timing (SDR104, SDR50, SD25, SDR12) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tis SDMMC_CMD/SDMMC_DATA[7:0] input setup (SDR104) 1.4 — — ns
SDMMC_CMD/SDMMC_DATA[7:0] input setup (SDR50) 3 — — ns
SDMMC_CMD/SDMMC_DATA[7:0] input setup (SDR25) 6 — — ns
SDMMC_CMD/SDMMC_DATA[7:0] input setup (SDR12) 5 — — ns
Tih SDMMC_CMD/SDMMC_DATA[7:0] input hold (SDR104) 0.8 — — ns
SDMMC_CMD/SDMMC_DATA[7:0] input hold (SDR50) 0.8 — — ns
SDMMC_CMD/SDMMC_DATA[7:0] input hold (SDR25) 2 — — ns
SDMMC_CMD/SDMMC_DATA[7:0] input hold (SDR12) 5 — — ns
Figure 8. SD Input (SDR104, SDR50, SD25, SDR12) Timing Diagram
Table 84.  SD Output Timing (SDR50, SDR25, SDR12) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Todly SDMMC_CMD/SDMMC_DATA[7:0] output delay (SDR50) — — 7.5 ns
SDMMC_CMD/SDMMC_DATA[7:0] output delay (SDR25, SDR12) — — 14 ns
Tohld SDMMC_CMD/SDMMC_DATA[7:0] output hold 1.5 — — ns
Figure 9. SD Output (SDR50, SDR25, SDR12) Timing Diagram
Table 85.  SD Output Timing (SDR104) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Top SDMMC_CMD/SDMMC_DATA[7:0] output phase 0 — 10 ns
∆Top SDMMC_CMD/SDMMC_DATA[7:0] output delay variation due to temperature change after tuning –350 — 1,550 ps
Todw SDMMC_CMD/SDMMC_DATA[7:0] output hold 3 — — ns
Figure 10. SD Output (SDR104) Timing Diagram
Table 86.  SD Timing (DDR50) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tisu SDMMC_CMD input setup 6 — — ns
Tih SDMMC_CMD input hold 0.8 — — ns
Todly SDMMC_CMD output delay — — 13.7 ns
Toh SDMMC_CMD output hold 1.5 — — ns
Tisu2x SDMMC_DATA[7:0] input setup 3 — — ns
Tih2x SDMMC_DATA[7:0] input hold 0.8 — — ns
Todly2x SDMMC_DATA[7:0] output delay — — 7 ns
Todly2x SDMMC_DATA[7:0] output hold 1.5 — — ns
Figure 11. SD (DDR50) Timing Diagram
Table 87.  eMMC Timing (Legacy, HS50 SDR) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tisu EMMC_CMD_DATA input setup (Legacy) 3 — — ns
EMMC_CMD_DATA input setup (HS50 SDR) 3 — — ns
Tih EMMC_CMD DATA_input hold (Legacy) 3 — — ns
EMMC_CMD DATA_input hold (HS50 SDR) 3 — — ns
Todly EMMC_CMD_DATA output delay (Legacy) — — 13.7 ns
EMMC_CMD_DATA output delay (HS50 SDR) — — 13.7 ns
Toh EMMC_CMD_DATA output hold (Legacy) 8.3 — — ns
EMMC_CMD DATA_output hold (HS50 SDR) 2.5 — — ns
Figure 12. eMMC (Legacy, HS50 SDR) Timing Diagram
Table 88.  eMMC Timing (HS100 DDR) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tisu_ddr EMMC_CMD_DATA input setup 2.5 — — ns
Tih_ddr EMMC_CMD DATA_input hold 2.5 — — ns
Todly_ddr EMMC_CMD_DATA output delay (max=delay, min=hold) 1.5 — 7 ns
Figure 13. eMMC (HS100 DDR) Timing Diagram
Table 89.  eMMC Timing (HS200 SDR) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tisu EMMC_CMD_DATA input setup 1.4 — — ns
Tih EMMC_CMD DATA_input hold 0.8 — — ns
Tph SDMMC_CMD/SDMMC_DATA[7:0] output phase 0 — 10 ns
∆Tph SDMMC_CMD/SDMMC_DATA[7:0] output delay variation due to temperature change after tuning –350 — 1,550 ps
Tvw SDMMC_CMD/SDMMC_DATA[7:0] output hold 3 — — ns
Figure 14. eMMC Input (HS200 SDR) Timing Diagram
Figure 15. eMMC Output (HS200 SDR) Timing Diagram
Table 90.  eMMC Timing (HS400 DDR) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tisu_ddr EMMC_CMD_DATA input setup 0.4 — — ns
Tih_ddr EMMC_CMD DATA_input hold 0.4 — — ns
Trq SDMMC_CMD/SDMMC_DATA[7:0] output phase 0 — 10 ns
∆Trq SDMMC_CMD/SDMMC_DATA[7:0] output delay variation due to temperature change after tuning –350 — 200 ps
Trqh SDMMC_CMD/SDMMC_DATA[7:0] output hold 2 — — ns
Figure 16. eMMC Input (HS400 DDR) Timing Diagram
Figure 17. eMMC Output (HS400 DDR) Timing Diagram
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