Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

HPS SD/eMMC Timing Characteristics

Table 82.  HPS Secure Digital (SD)/Embedded MultiMediaCard (eMMC) Timing Requirements

Supports SD devices up to V6.1. Supports SDIO devices up to V4.1. Supports SD/eMMC devices up to V5.1.

These timings apply to SD, MMC, and eMMC cards operating at 1.8 V.

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit
Tsdmmc_cclk SD SDMMC_CCLK clock period Identification mode, 400 kHz 2,500 ns
SDR12, 25 MHz 40 ns
SDR25, 50 MHz 20 ns
SDR50, 100 MHz 10 ns
SDR104, <200 MHz 5 ns
DDR50, 50 MHz 20 ns
eMMC SDMMC_CCLK clock period Legacy, 25MB/s, 25 MHz 40 ns
HS_SDR, 50MB/s, 50 MHz 20 ns
HS_DDR, 100MB/s, 50 MHz 20 ns
HS200, SDR, 200MB/s, 200 MHz 5 ns
HS400, DDR, 400MB/s, 200 MHz 5 ns
Tdutycycle SDMMC_CCLK duty cycle 45 50 55 %
Tsdmmc_cclk_jitter SDMMC_CCLK output jitter 2 %
Tsdmmc_clk Internal reference clock before division by 4 (200 MHz) 5 ns
None of the HPS I/Os supports 3 V mode, while SD/MMC cards must operate at 3 V at power on. eMMC devices can operate at 1.8 V at power on.
Note: SD cards power up at 3 V. To support SD, your design must include a level shifter between the SD card and the HPS SD/MMC interface.
Table 83.  SD Input Timing (SDR104, SDR50, SDR25, SDR12) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tis SDMMC_CMD/SDMMC_DATA[7:0] input setup (SDR104) 1.4 ns
SDMMC_CMD/SDMMC_DATA[7:0] input setup (SDR50) 3 ns
SDMMC_CMD/SDMMC_DATA[7:0] input setup (SDR25) 6 ns
SDMMC_CMD/SDMMC_DATA[7:0] input setup (SDR12) 5 ns
Tih SDMMC_CMD/SDMMC_DATA[7:0] input hold (SDR104) 0.8 ns
SDMMC_CMD/SDMMC_DATA[7:0] input hold (SDR50) 0.8 ns
SDMMC_CMD/SDMMC_DATA[7:0] input hold (SDR25) 2 ns
SDMMC_CMD/SDMMC_DATA[7:0] input hold (SDR12) 5 ns
Figure 8. SD Input (SDR104, SDR50, SDR25, SDR12) Timing Diagram
Table 84.  SD Output Timing (SDR50, SDR25, SDR12) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Todly SDMMC_CMD/SDMMC_DATA[7:0] output delay (SDR50) 7.5 ns
SDMMC_CMD/SDMMC_DATA[7:0] output delay (SDR25, SDR12) 14 ns
Tohld SDMMC_CMD/SDMMC_DATA[7:0] output hold 1.5 ns
Figure 9. SD Output (SDR50, SDR25, SDR12) Timing Diagram
Table 85.  SD Output Timing (SDR104) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Top SDMMC_CMD/SDMMC_DATA[7:0] output phase 0 10 ns
∆Top SDMMC_CMD/SDMMC_DATA[7:0] output delay variation due to temperature change after tuning –350 1,550 ps
Todw SDMMC_CMD/SDMMC_DATA[7:0] output hold 3 ns
Figure 10. SD Output (SDR104) Timing Diagram
Table 86.  SD Timing (DDR50) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tisu SDMMC_CMD input setup 6 ns
Tih SDMMC_CMD input hold 0.8 ns
Todly SDMMC_CMD output delay 13.7 ns
Toh SDMMC_CMD output hold 1.5 ns
Tisu2x SDMMC_DATA[7:0] input setup 3 ns
Tih2x SDMMC_DATA[7:0] input hold 0.8 ns
Todly2x SDMMC_DATA[7:0] output delay 7 ns
Todly2x SDMMC_DATA[7:0] output hold 1.5 ns
Figure 11. SD (DDR50) Timing Diagram
Table 87.  eMMC Timing (Legacy, HS_SDR) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tisu EMMC_CMD_DATA input setup (Legacy) 3 ns
EMMC_CMD_DATA input setup (HS_SDR) 3 ns
Tih EMMC_CMD DATA_input hold (Legacy) 3 ns
EMMC_CMD DATA_input hold (HS_SDR) 3 ns
Todly EMMC_CMD_DATA output delay (Legacy) 13.7 ns
EMMC_CMD_DATA output delay (HS_SDR) 13.7 ns
Toh EMMC_CMD_DATA output hold (Legacy) 8.3 ns
EMMC_CMD DATA_output hold (HS_SDR) 2.5 ns
Figure 12. eMMC (Legacy, HS_SDR) Timing Diagram
Table 88.  eMMC Timing (HS_DDR) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tisu_ddr EMMC_CMD_DATA input setup 2.5 ns
Tih_ddr EMMC_CMD DATA_input hold 2.5 ns
Todly_ddr EMMC_CMD_DATA output delay (max=delay, min=hold) 1.5 7 ns
Figure 13. eMMC (HS_DDR) Timing Diagram
Table 89.  eMMC Timing (HS200) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tisu EMMC_CMD_DATA input setup 1.4 ns
Tih EMMC_CMD DATA_input hold 0.8 ns
Tph SDMMC_CMD/SDMMC_DATA[7:0] output phase 0 10 ns
∆Tph SDMMC_CMD/SDMMC_DATA[7:0] output delay variation due to temperature change after tuning –350 1,550 ps
Tvw SDMMC_CMD/SDMMC_DATA[7:0] output hold 3 ns
Figure 14. eMMC Input (HS200) Timing Diagram
Figure 15. eMMC Output (HS200) Timing Diagram
Table 90.  eMMC Timing (HS400) For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tisu_ddr EMMC_CMD_DATA input setup 0.4 ns
Tih_ddr EMMC_CMD DATA_input hold 0.4 ns
Trq SDMMC_CMD/SDMMC_DATA[7:0] output phase 0 10 ns
∆Trq SDMMC_CMD/SDMMC_DATA[7:0] output delay variation due to temperature change after tuning –350 200 ps
Trqh SDMMC_CMD/SDMMC_DATA[7:0] output hold 2 ns
Figure 16. eMMC Input (HS400) Timing Diagram
Figure 17. eMMC Output (HS400) Timing Diagram