Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

HPS SPI Timing Characteristics

Table 80.  SPI Master Timing Requirements

You can adjust the input delay timing by programming the rx_sample_dly register.

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit
Tspi_ref_clk The period of the SPI internal reference clock, sourced from l4_main_clk 2.5 — — ns
Tclk SPIM_CLK clock period 16.67 — — ns
Tdutycycle SPIM_CLK duty cycle 45 50 55 %
Tck_jitter SPIM_CLK output jitter — — 2 %
Tdio Master-out slave-in (MOSI) output skew –3 — 2 ns
Tdssfrst 144 SPI_SS_N asserted to first SPIM_CLK edge (1.5 × Tclk) – 2 — — ns
Tdsslst 144 Last SPIM_CLK edge to SPI_SS_N deasserted Tclk – 2 — — ns
Tsu 145 SPIM_MISO setup time with respect to SPIM_CLK capture edge 5.0 – (rx_sample_dly x Tspi_ref_clk)146 — — ns
Th 145 Input hold in respect to SPIM_CLK capture edge 1.3 + (rx_sample_dly x Tspi_ref_clk)146 — — ns
Figure 4. SPI Master Output Timing Diagram
Figure 5. SPI Master Input Timing Diagram
Table 81.  SPI Slave Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tspi_ref_clk The period of the SPI internal reference clock, sourced from l4_main_clk 2.5 — — ns
Tclk SPIM_CLK clock period 30 — — ns
Tdutycycle SPIM_CLK duty cycle 45 50 55 %
Td Master-in slave-out (MISO) output skew (2 × Tspi_ref_clk) + 3 — (3 × Tspi_ref_clk) + 11 ns
Tsu Master-out slave-in (MOSI) setup time 4 — — ns
Th Master-out slave-in (MOSI) hold time 9 — — ns
Tsuss SPI_SS_N asserted to first SPIM_CLK edge Tspi_ref_clk + 4.2 — — ns
Thss Last SPIM_CLK edge to SPI_SS_N deasserted Tspi_ref_clk + 4.2 — — ns
Figure 6. SPI Slave Output Timing Diagram
Figure 7. SPI Slave Input Timing Diagram
144 SPI_SS_N behavior differs depending on Motorola SPI protocols, Texas Instruments Synchronous Serial Protocols, or National Semiconductor Microwire operational mode.
145 The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for Texas Instruments Synchronous Serial Protocols, the capture edge is the falling edge; for National Semiconductor Microwire, the capture edge is the rising edge.
146 Valid values of rx_sample_dly range from 1 to 64 (units are in Tspi_ref_clk steps).
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