Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

HPS SPI Timing Characteristics

Table 80.  SPI Master Timing Requirements

You can adjust the input delay timing by programming the rx_sample_dly register.

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit
Tspi_ref_clk The period of the SPI internal reference clock, sourced from l4_main_clk 2.5 ns
Tclk SPIM_CLK clock period 16.67 ns
Tdutycycle SPIM_CLK duty cycle 45 50 55 %
Tck_jitter SPIM_CLK output jitter 2 %
Tdio Master-out slave-in (MOSI) output skew –3 2 ns
Tdssfrst 144 SPI_SS_N asserted to first SPIM_CLK edge (1.5 × Tclk) – 2 ns
Tdsslst 144 Last SPIM_CLK edge to SPI_SS_N deasserted Tclk – 2 ns
Tsu 145 SPIM_MISO setup time with respect to SPIM_CLK capture edge 5.0 – (rx_sample_dly x Tspi_ref_clk)146 ns
Th 145 Input hold in respect to SPIM_CLK capture edge 1.3 + (rx_sample_dly x Tspi_ref_clk)146 ns
Figure 4. SPI Master Output Timing Diagram
Figure 5. SPI Master Input Timing Diagram
Table 81.  SPI Slave Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tspi_ref_clk The period of the SPI internal reference clock, sourced from l4_main_clk 2.5 ns
Tclk SPIM_CLK clock period 30 ns
Tdutycycle SPIM_CLK duty cycle 45 50 55 %
Td Master-in slave-out (MISO) output skew (2 × Tspi_ref_clk) + 3 (3 × Tspi_ref_clk) + 11 ns
Tsu Master-out slave-in (MOSI) setup time 4 ns
Th Master-out slave-in (MOSI) hold time 9 ns
Tsuss SPI_SS_N asserted to first SPIM_CLK edge Tspi_ref_clk + 4.2 ns
Thss Last SPIM_CLK edge to SPI_SS_N deasserted Tspi_ref_clk + 4.2 ns
Figure 6. SPI Slave Output Timing Diagram
Figure 7. SPI Slave Input Timing Diagram
144 SPI_SS_N behavior differs depending on Motorola SPI protocols, Texas Instruments Synchronous Serial Protocols, or National Semiconductor Microwire operational mode.
145 The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for Texas Instruments Synchronous Serial Protocols, the capture edge is the falling edge; for National Semiconductor Microwire, the capture edge is the rising edge.
146 Valid values of rx_sample_dly range from 1 to 64 (units are in Tspi_ref_clk steps).