Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

GTS Transceiver Reference Clock Specifications

Table 68.  GTS Transceiver and System PLL Reference Clock Input Specifications For specification status, see the Data Sheet Status table
Symbol Description Condition Min Typical Max Unit
— Supported I/O standards Dedicated reference clock pin CML, HCSL
FREF Reference clock operating frequency — 100127 — 380 MHz
TREF-DUTY Duty cycle — 45 50 55 %
TREF-RISE/FALL Rise and fall time (as percentage of period) 20% – 80% — — 0.15 TREF
SSC Spread-spectrum downspread PCIe* — –5,000 to 0 — ppm
TREF-SINGLEEND-SKEW Skew between REFCLKP and REFCLKN — — — 50 ps
ZREF-DIFF-DC Reference clock differential input impedance – terminated mode — 80 100 120 Ω
Vmin-ABS Absolute Vmin — –0.15 — — V
Vmax-ABS Absolute Vmax — — — 0.85 V
VREFIN-DIFF-AC Input reference clock differential peak-to-peak voltage when AC-coupled on board — 0.6 1.2 1.7 V
VREFIN-IL-DC Input reference clock input low voltage when DC-coupled on board — –0.15 0 0.15 V
VREFIN-IH-DC Input reference clock input high voltage when DC-coupled on board    — 0.66 0.7 0.85 V
VREFIN-CM-AC Input reference clock common-mode voltage when AC-coupled on board — Set on chip V
VREFIN-CM-DC Input reference clock common-mode voltage when DC-coupled on board — 0.255 0.35 0.5 V
PNREF Transmitter REFCLK phase noise (156.25 MHz)128 127 10 kHz — — –130 dBc/Hz
100 kHz — — –138 dBc/Hz
500 kHz — — –138 dBc/Hz
3 MHz — — –140 dBc/Hz
10 MHz — — –144 dBc/Hz
20 MHz — — –146 dBc/Hz
1 GHz — — –146 dBc/Hz
VREFIN-RJ-RMS RMS jitter integrated from 10 kHz – 20 MHz including spurs — — — 522 fs
VREFIN-PPM-ERROR Reference clock frequency error — –350 + SSC — +350 + SSC ppm
RCOMP External resistor for calibration — — 499 ± 0.1% — Ω
Table 69.  System PLL Reference Clock (Using HVIO) Specifications For specification status, see the Data Sheet Status table
Symbol Description Condition Min Typical Max Unit
FREF Clock input frequency Powered by VCCIO_HVIO 25 — 125 MHz
TREF-DUTY Clock input duty cycle 45 50 55 %
Table 70.  GTS Transceiver Reference Clock Output Driver Specifications For specification status, see the Data Sheet Status table
Symbol Description Condition Min Typical Max Unit
FREF_OUT Reference clock operating frequency — 25 — 380 MHz
TREF-DUTY_OUT Duty cycle — 45 50 55 %
TREF-RISE_OUT/FALL_OUT Rise and fall time (as percentage of period) 20% – 80% — — 0.15 TREF
TREF-SINGLEEND-SKEW Skew between REFCLKP and REFCLKN — — — 50 ps
ZREF-DIFF-DC_OUT Reference clock differential output impedance – terminated mode — 80 100 120 Ω
VREF-DIFF-AC_OUT Output reference clock differential peak to peak voltage when AC-coupled on board — 0.9 1 1.1 V
VREF-CM-OUT Output reference clock common-mode — 0.45 0.5 0.55 V
127 This value is 100 MHz for down spread spectrum clocking (SSC). This value can also be 25 MHz for HDMI rate of less than 1 Gbps.
128 To calculate the REFCLK phase noise requirement at frequencies other than 156.25 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 156.25 MHz + 20 × log(f/156.25 MHz).
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