Visible to Intel only — GUID: eem1662081231853
Ixiasoft
HSIO Single-Ended I/O Standards Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
HSIO Single-Ended LVSTL I/O Standards Specifications
HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications
HSIO Differential POD I/O Standards Specifications
HSIO Differential LVSTL I/O Standards Specifications
HSIO Differential I/O Standards Specifications
MIPI D-PHY I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/eMMC Timing Characteristics
HPS USB 2.0 Timing Characteristics
HPS USB 3.1 Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS I3C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: eem1662081231853
Ixiasoft
GTS Transceiver Reference Clock Specifications
Symbol | Description | Condition | Min | Typical | Max | Unit |
---|---|---|---|---|---|---|
— | Supported I/O standards | Dedicated reference clock pin | CML, HCSL | |||
FREF | Reference clock operating frequency | — | 100127 | — | 380 | MHz |
TREF-DUTY | Duty cycle | — | 45 | 50 | 55 | % |
TREF-RISE/FALL | Rise and fall time (as percentage of period) | 20% – 80% | — | — | 0.15 | TREF |
SSC | Spread-spectrum downspread | PCIe* | — | –5,000 to 0 | — | ppm |
TREF-SINGLEEND-SKEW | Skew between REFCLKP and REFCLKN | — | — | — | 50 | ps |
ZREF-DIFF-DC | Reference clock differential input impedance – terminated mode | — | 80 | 100 | 120 | Ω |
Vmin-ABS | Absolute Vmin | — | –0.15 | — | — | V |
Vmax-ABS | Absolute Vmax | — | — | — | 0.85 | V |
VREFIN-DIFF-AC | Input reference clock differential peak-to-peak voltage when AC-coupled on board | — | 0.6 | 1.2 | 1.7 | V |
VREFIN-IL-DC | Input reference clock input low voltage when DC-coupled on board | — | –0.15 | 0 | 0.15 | V |
VREFIN-IH-DC | Input reference clock input high voltage when DC-coupled on board | — | 0.66 | 0.7 | 0.85 | V |
VREFIN-CM-AC | Input reference clock common-mode voltage when AC-coupled on board | — | Set on chip | V | ||
VREFIN-CM-DC | Input reference clock common-mode voltage when DC-coupled on board | — | 0.255 | 0.35 | 0.5 | V |
PNREF | Transmitter REFCLK phase noise (156.25 MHz)128 127 | 10 kHz | — | — | –130 | dBc/Hz |
100 kHz | — | — | –138 | dBc/Hz | ||
500 kHz | — | — | –138 | dBc/Hz | ||
3 MHz | — | — | –140 | dBc/Hz | ||
10 MHz | — | — | –144 | dBc/Hz | ||
20 MHz | — | — | –146 | dBc/Hz | ||
1 GHz | — | — | –146 | dBc/Hz | ||
VREFIN-RJ-RMS | RMS jitter integrated from 10 kHz – 20 MHz including spurs | — | — | — | 522 | fs |
VREFIN-PPM-ERROR | Reference clock frequency error | — | –350 + SSC | — | +350 + SSC | ppm |
RCOMP | External resistor for calibration | — | — | 499 ± 0.1% | — | Ω |
Symbol | Description | Condition | Min | Typical | Max | Unit |
---|---|---|---|---|---|---|
FREF | Clock input frequency | Powered by VCCIO_HVIO | 25 | — | 125 | MHz |
TREF-DUTY | Clock input duty cycle | 45 | 50 | 55 | % |
Symbol | Description | Condition | Min | Typical | Max | Unit |
---|---|---|---|---|---|---|
FREF_OUT | Reference clock operating frequency | — | 25 | — | 380 | MHz |
TREF-DUTY_OUT | Duty cycle | — | 45 | 50 | 55 | % |
TREF-RISE_OUT/FALL_OUT | Rise and fall time (as percentage of period) | 20% – 80% | — | — | 0.15 | TREF |
TREF-SINGLEEND-SKEW | Skew between REFCLKP and REFCLKN | — | — | — | 50 | ps |
ZREF-DIFF-DC_OUT | Reference clock differential output impedance – terminated mode | — | 80 | 100 | 120 | Ω |
VREF-DIFF-AC_OUT | Output reference clock differential peak to peak voltage when AC-coupled on board | — | 0.9 | 1 | 1.1 | V |
VREF-CM-OUT | Output reference clock common-mode | — | 0.45 | 0.5 | 0.55 | V |
127 This value is 100 MHz for down spread spectrum clocking (SSC). This value can also be 25 MHz for HDMI rate of less than 1 Gbps.
128 To calculate the REFCLK phase noise requirement at frequencies other than 156.25 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 156.25 MHz + 20 × log(f/156.25 MHz).