Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

POR Specifications

Power-on reset (POR) delay is defined as the delay between last power rail (VCCIO_SDM) monitored by POR circuitry reached the minimum operating voltage to the time the device is ready to begin configuration.

Table 107.  POR Delay Specifications For specification status, see the Data Sheet Status table
POR Delay Minimum Maximum Unit
AS (Normal mode), AVST ×8, AVST ×16 11.5 20.2 ms
AS (Fast mode) 1.5 7.6 ms