Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

Electrical Compliance

Table 73.  Electrical Compliance List For specification status, see the Data Sheet Status table
Specification/Clause Protocol Lane Rate (Gbps)
E-Series Device Group B E-Series Device Group A, D-Series
XFP MSA XFI 10.3125 10.3125
IEEE 802.3ba-2010 XLPPI 10.3125 10.3125
Serial-GMII Specification V1.7 1GE SGMII 1.25 1.25
IEEE 802.3ba XLAUI 10.3125 10.3125
IEEE 802.3ba CAUI-10 10.3125 10.3125
IEEE 802.3by 25GAUI-C2C/C2M — 1x25.78125
IEEE 802.3ap 2007 10GBASE-KR 10.3125 10.3125
IEEE 802.3by 111/110 25GBASE-KR/CR — 25.78125
IEEE 803.3ap-2007

IEEE 802.3an-2006

 1000BASE-KX/CX 1.25 1.25
CEI 4.0 CEI-11G SR/MR/LR 9.95 – 11.2 9.95 – 11.2
CEI-6G SR/LR 4.976 – 6.375 4.976 – 6.375
G.709

G.sup56

G.sup43

G.sup58

 OTU1 — 1.327451, 2.666
OTU2 — 10.709, 11.049, 11.270
OTU2e — 11.095
OTU2f — 11.317, 11.846, 12.639
OTU4 OTL4.4 — 4x27.952493
OTU4 OTLC.4 — 4x28.076177
PCIe* BASE 4.0

PIPE 4.4.1

 PCIe* 3.0 , PCIe* 4.0 8, 16138 8, 16
SMPTE 259M SDI SD 0.27 0.27
SMPTE 292M SDI HD 1.485/1.483 1.485/1.483
SMPTE ST 424 SDI 3G 2.97/2.967 2.97/2.967
SMPTE ST 2081 SDI 6G 5.94/5.934 5.94/5.934
SMPTE ST 2082 SDI 12G 11.88/11.868 11.88/11.868
CPRI V7.0 CPRI 1.2288 1.2288
2.4576 2.4576
3.072 3.072
4.9152 4.9152
6.144 6.144
8.1101 8.1101
9.8304 9.8304
10.1376 10.1376
— 24.33024
JESD204B JESD204B up to 17.16 up to 19.66
JESD204C JESD204C up to 17.16 up to 28.1
DP 2.0 DisplayPort 1.4 1.62 1.62
2.7 2.7
5.4 5.4
8.1 8.1
DisplayPort 2.0 10 10
13.5 13.5
— 20
FC-PI-2 Fiber Channel 1.0625 1.0625
2.125 2.125
FC-PI-5 4.25 4.25
8.5 8.5
10GFC 10.518 10.518
FC-PI-5 14.025 14.025
FC-PI-6 — 28.05
— 4x28.05
Serial ATA revision 3.5a

T10/BSR INCITS 519

 Sata Gen 3 1.5 – 6 1.5 – 6
SAS 1.5 – 12.0 1.5 – 22.5
G.984 GPON/EPON — 1.244, 1.250, 2.488, 9.952, 10.313, 25
CEI-6G-SR Interlaken 6.25 6.25
CEI-11G-SR 10.3125 10.3125
CEI-11G-SR+ 12.5 12.5
OIF-28G MR (OIF-CEI3.0) — 25.78125
HDMI 1.4 HDMI 3.4 3.4
HDMI 2.0 6 6
HDMI 2.1 up to 12 up to 12
SLVS-EC Specification Version 1.0 SLVS-EC RX 2.376 2.376
SLVS-EC Specification Version 2.0 5 5
SFF-8402 SFP+ 9.95 – 11.2 9.95 – 11.2
SFF-8431 4.1
SFF-8431 Rev 4.1
SFF-8418
USB 3.1, USB 3.2 USB 3.1 Gen 1 5 5
USB 3.2 Gen 2 139 — 10 139
RapidIO™ Interconnect Specification SRIO 2 – 16 2 – 16
138 PCIe* 4.0 is supported for –4S (VCC = 0.8 V) devices only.
139 Gen 2 is supported using transceiver PMA only, with soft PIPE PCS and USB 3.2 controller in core fabric.
Level Two Title