Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.

Table 53.  D-Series FPGAs Memory Block Performance Specifications For specification status, see the Data Sheet Status table
Memory Mode Performance Unit
–1V –2V –3V
MLAB Single-port RAM/ROM

Simple dual-port RAM

 1,000 782 667 MHz
Simple dual-port RAM with read-during-write option set to New Data or Old Data 630 510 460 MHz
M20K block96 Single-port RAM/ROM

Simple dual-port RAM

 1000 (HS)

850 (LP)

 782 (HS)

664 (LP)

 667 (HS)

567 (LP)

 MHz
Simple dual-port RAM, coherent read enabled 1000 (HS)

850 (LP)

 782 (HS)

664 (LP)

 667 (HS)

567 (LP)

 MHz
Single-port RAM with the read-during-write option set to Old Data

Simple dual-port RAM with the read-during-write option set to Old Data

 800 (HS)

680 (LP)

 640 (HS)

540 (LP)

 560 (HS)

476 (LP)

 MHz
Simple dual-port RAM with ECC enabled, 512 × 32 600 (HS)

500 (LP)

 480 (HS)

400 (LP)

 420 (HS)

357 (LP)

 MHz
Simple dual-port RAM with ECC, optional pipeline registers enabled, 512 × 32 1000 (HS)

850 (LP)

 782 (HS)

664 (LP)

 667 (HS)

567 (LP)

 MHz
Dual-port ROM

True dual-port RAM

 600 (HS) 500 (HS) 420 (HS) MHz
Simple quad-port RAM 600 (HS) 500 (HS) 420 (HS) MHz
Table 54.  E-Series FPGAs Memory Block Performance Specifications For specification status, see the Data Sheet Status table
Memory Mode Performance Unit
–1V –2V, –2E –3V –4S –5S –6S, –6X
MLAB Single-port RAM/ROM

Simple dual-port RAM

 850 750 510 600 469 400 MHz
Simple dual-port RAM with read-during-write option set to New Data or Old Data 530 450 380 400 310 280 MHz
M20K block97 Single-port RAM/ROM

Simple dual-port RAM

 1000 (HS)

850 (LP)

 782 (HS)

664 (LP)

 667 (HS)

567 (LP)

 700 (HS)

595 (LP)

 550 (HS) 465 (HS) MHz
Simple dual-port RAM, coherent read enabled 1000 (HS)

850 (LP)

 782 (HS)

664 (LP)

 667 (HS)

567 (LP)

 700 (HS)

595 (LP)

 550 (HS) 465 (HS) MHz
Single-port RAM with the read-during-write option set to Old Data

Simple dual-port RAM with the read-during-write option set to Old Data

 800 (HS)

680 (LP)

 640 (HS)

540 (LP)

 560 (HS)

476 (LP)

 560 (HS)

475 (LP)

 440 (HS) 370 (HS) MHz
Simple dual-port RAM with ECC enabled, 512 × 32 600 (HS)

500 (LP)

 480 (HS)

400 (LP)

 420 (HS)

357 (LP)

 420 (HS)

355 (LP)

 330 (HS) 280 (HS) MHz
Simple dual-port RAM with ECC, optional pipeline registers enabled, 512 × 32 1000 (HS)

850 (LP)

 782 (HS)

664 (LP)

 667 (HS)

567 (LP)

 700 (HS)

595 (LP)

 550 (HS) 465 (HS) MHz
Dual-port ROM

True dual-port RAM

 600 (HS) 500 (HS) 420 (HS) 445 (HS) 335 (HS) 280 (HS) MHz
Simple quad-port RAM 600 (HS) 500 (HS) 420 (HS) 445 (HS) 335 (HS) 280 (HS) MHz
96 For M20K block, timing/power optimization feature is available. The available options are high speed (HS) and low power (LP).
97 For M20K block, timing/power optimization feature is available. The available options are high speed (HS) and low power (LP).
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