Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.

Table 53.  D-Series FPGAs Memory Block Performance Specifications For specification status, see the Data Sheet Status table
Memory Mode Performance Unit
–1V –2V –3V
MLAB Single-port RAM/ROM

Simple dual-port RAM

1,000 782 667 MHz
Simple dual-port RAM with read-during-write option set to New Data or Old Data 630 510 460 MHz
M20K block96 Single-port RAM/ROM

Simple dual-port RAM

1000 (HS)

850 (LP)

782 (HS)

664 (LP)

667 (HS)

567 (LP)

MHz
Simple dual-port RAM, coherent read enabled 1000 (HS)

850 (LP)

782 (HS)

664 (LP)

667 (HS)

567 (LP)

MHz
Single-port RAM with the read-during-write option set to Old Data

Simple dual-port RAM with the read-during-write option set to Old Data

800 (HS)

680 (LP)

640 (HS)

540 (LP)

560 (HS)

476 (LP)

MHz
Simple dual-port RAM with ECC enabled, 512 × 32 600 (HS)

500 (LP)

480 (HS)

400 (LP)

420 (HS)

357 (LP)

MHz
Simple dual-port RAM with ECC, optional pipeline registers enabled, 512 × 32 1000 (HS)

850 (LP)

782 (HS)

664 (LP)

667 (HS)

567 (LP)

MHz
Dual-port ROM

True dual-port RAM

600 (HS) 500 (HS) 420 (HS) MHz
Simple quad-port RAM 600 (HS) 500 (HS) 420 (HS) MHz
Table 54.  E-Series FPGAs Memory Block Performance Specifications For specification status, see the Data Sheet Status table
Memory Mode Performance Unit
–1V –2V, –2E –3V –4S –5S –6S, –6X
MLAB Single-port RAM/ROM

Simple dual-port RAM

850 750 510 600 469 400 MHz
Simple dual-port RAM with read-during-write option set to New Data or Old Data 530 450 380 400 310 280 MHz
M20K block97 Single-port RAM/ROM

Simple dual-port RAM

1000 (HS)

850 (LP)

782 (HS)

664 (LP)

667 (HS)

567 (LP)

700 (HS)

595 (LP)

550 (HS) 465 (HS) MHz
Simple dual-port RAM, coherent read enabled 1000 (HS)

850 (LP)

782 (HS)

664 (LP)

667 (HS)

567 (LP)

700 (HS)

595 (LP)

550 (HS) 465 (HS) MHz
Single-port RAM with the read-during-write option set to Old Data

Simple dual-port RAM with the read-during-write option set to Old Data

800 (HS)

680 (LP)

640 (HS)

540 (LP)

560 (HS)

476 (LP)

560 (HS)

475 (LP)

440 (HS) 370 (HS) MHz
Simple dual-port RAM with ECC enabled, 512 × 32 600 (HS)

500 (LP)

480 (HS)

400 (LP)

420 (HS)

357 (LP)

420 (HS)

355 (LP)

330 (HS) 280 (HS) MHz
Simple dual-port RAM with ECC, optional pipeline registers enabled, 512 × 32 1000 (HS)

850 (LP)

782 (HS)

664 (LP)

667 (HS)

567 (LP)

700 (HS)

595 (LP)

550 (HS) 465 (HS) MHz
Dual-port ROM

True dual-port RAM

600 (HS) 500 (HS) 420 (HS) 445 (HS) 335 (HS) 280 (HS) MHz
Simple quad-port RAM 600 (HS) 500 (HS) 420 (HS) 445 (HS) 335 (HS) 280 (HS) MHz
96 For M20K block, timing/power optimization feature is available. The available options are high speed (HS) and low power (LP).
97 For M20K block, timing/power optimization feature is available. The available options are high speed (HS) and low power (LP).