Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

HVIO Internal Weak Pull-Up and Pull-Down Resistor

Only input and bidirectional pins in HVIO bank have an option to enable weak pull-up and pull-down when using LVCMOS I/O standard.

Table 25.  HVIO Internal Weak Pull-Up and Pull-Down Resistor Values For specification status, see the Data Sheet Status table
Symbol Description Condition (V) Min Typ Max Unit
20 kΩ RPU, 20 kΩ RPD Value of the I/O pin pull-up and pull-down resistor during user mode if you have enabled the programmable pull-up or pull-down resistor option. VCCIO_HVIO = 1.8, 2.5, 3.3 ±3% 15 20 30