Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

HPS I2C Timing Characteristics

Table 96.  HPS I2C Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Standard Mode Fast Mode Unit
Min Max Min Max
Tclk Serial clock (SCL) clock period 10 2.5 μs
Tclk_jitter I2C clock output jitter 2 2 %
THIGH 150 SCL high period 4151 0.6152 μs
TLOW 153 SCL low period 4.7154 1.3155 μs
TSU_DAT Setup time for serial data line (SDA) data to SCL 0.25 0.1 μs
THD_DAT 156 Hold time for SCL to SDA data 0 3.15 0 0.6 μs
TVD_DAT and TVD_ACK 157 SCL to SDA output data delay 3.45158 0.9159 μs
TSU_STA Setup time for a repeated start condition 4.7 0.6 μs
THD_STA Hold time for a repeated start condition 4 0.6 μs
TSU_STO Setup time for a stop condition 4 0.6 μs
TBUF SDA high pulse duration between STOP and START 4.7 1.3 μs
Tscl_r 160 SCL rise time 1,000 20 300 ns
Tscl_f 160 SCL fall time 300 6.54 300 ns
Tsda_r 160 SDA rise time 1,000 20 300 ns
Tsda_f 160 SDA fall time 300 6.54 300 ns
Figure 23. I2C Timing Diagram
150 You can adjust THIGH using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
151 The recommended minimum setting for ic_ss_scl_hcnt is 428. Refer to the SCL_High_time equation in the Hard Processor System Technical Reference Manual.
152 The recommended minimum setting for ic_fs_scl_hcnt is 75. Refer to the SCL_High_time equation in the Hard Processor System Technical Reference Manual.
153 You can adjust TLOW using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
154 The recommended minimum setting for ic_ss_scl_lcnt is 464. Refer to the SCL_Low_time equation in the Hard Processor System Technical Reference Manual.
155 The recommended minimum setting for ic_fs_scl_lcnt is 163. Refer to the SCL_Low_time equation in the Hard Processor System Technical Reference Manual.
156 THD_DAT is affected by the rise and fall time.
157 TVD_DAT and TVD_ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).
158 Use maximum SDA_HOLD = 240 to be within the specification.
159 Use maximum SDA_HOLD = 60 to be within the specification.
160 Rise and fall time parameters vary depending on external factors such as the characteristics of the I/O driver, pull-up resistor value, and total capacitance on the transmission line.