Visible to Intel only — GUID: wek1662081501315
Ixiasoft
HSIO Single-Ended I/O Standards Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
HSIO Single-Ended LVSTL I/O Standards Specifications
HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications
HSIO Differential POD I/O Standards Specifications
HSIO Differential LVSTL I/O Standards Specifications
HSIO Differential I/O Standards Specifications
MIPI D-PHY I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/eMMC Timing Characteristics
HPS USB 2.0 Timing Characteristics
HPS USB 3.1 Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS I3C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: wek1662081501315
Ixiasoft
General Configuration Timing Specifications
Symbol | Description | Requirement | Unit | |
---|---|---|---|---|
Min | Max | |||
tCF12ST1 | nCONFIG high to nSTATUS high | — | 20 | ms |
tCF02ST0 170 | nCONFIG low to nSTATUS low | — | 400 | ms |
tST0 | nSTATUS low pulse during configuration error | 0.5 | 10 | ms |
tCD2UM 171 | CONF_DONE high to user mode | — | 5 | ms |
tST12CF0 | Minimum time to drive nCONFIG from high to low after nSTATUS transitions from low to high | 0 | — | ms |
tST02CF1 | Minimum time to drive nCONFIG from low to high after nSTATUS transitions from high to low | 0 | — | ms |
Figure 48. General Configuration Timing Diagram
170 You need to drive nCONFIG low pulse by referring to maximum value if nSTATUS cannot be monitored by host.
171 This specification is the initialization time that indicates the time from CONF_DONE signal goes high to INIT_DONE signal goes high.