Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

HSIO Single-Ended I/O Standards Specifications

Table 31.  HSIO Single-Ended I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) VIL (V) VIH (V) VOL (V)62 VOH (V)62
Min Typ Max Min Max Min Max63 Max Min
1.3 V LVCMOS 1.261 1.3 1.339 –0.3 0.35 × VCCIO_PIO 0.65 × VCCIO_PIO VCCIO_PIO + 0.25 0.25 × VCCIO_PIO 0.75 × VCCIO_PIO
1.2 V LVCMOS 1.14 1.2 1.26 –0.3 0.35 × VCCIO_PIO 0.65 × VCCIO_PIO VCCIO_PIO + 0.25 0.25 × VCCIO_PIO 0.75 × VCCIO_PIO
1.1 V LVCMOS 1.045 1.1 1.155 –0.3 0.35 × VCCIO_PIO 0.65 × VCCIO_PIO VCCIO_PIO + 0.25 0.25 × VCCIO_PIO 0.75 × VCCIO_PIO
1.05 V LVCMOS 0.9975 1.05 1.1025 –0.3 0.35 × VCCIO_PIO 0.65 × VCCIO_PIO VCCIO_PIO + 0.25 0.25 × VCCIO_PIO 0.75 × VCCIO_PIO
1.0 V LVCMOS 0.95 1 1.05 –0.3 0.35 × VCCIO_PIO 0.65 × VCCIO_PIO VCCIO_PIO + 0.25 0.25 × VCCIO_PIO 0.75 × VCCIO_PIO
62 Applicable to test condition of IOH and IOL at 2 mA.
63 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VIH(max) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V.