Agilex™ 5 FPGAs and SoCs Device Data Sheet

Download PDF
ID 813918
Date 8/05/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

DSP Block Specifications

Table 49.  D-Series FPGAs DSP Block Performance Specifications for Single DSP Block For specification status, see the Data Sheet Status table
Mode Performance Unit
–1V –2V –3V
Fixed-point 18 × 19 multiplication mode 768 655 574 MHz
Fixed-point 27 × 27 multiplication mode 768 655 574 MHz
Fixed-point 18 × 19 multiplier adder mode 768 655 574 MHz
Fixed-point 18 × 19 multiplier adder summed with 36-bit input mode 768 655 574 MHz
Fixed-point six 9 × 9 multiplier adder mode 768 655 574 MHz
FP32 floating-point multiplication mode 637 492 431 MHz
FP32 floating-point adder or subtract mode 637 492 431 MHz
FP32 floating-point multiplier adder or subtract mode 637 492 431 MHz
FP32 floating-point multiplier accumulate mode 637 492 431 MHz
Addition or subtraction of two FP16 floating-point multiplication mode 637 492 431 MHz
Sum/sub of two FP16 multiplications with FP32 (addition/subtraction) 637 492 431 MHz
Sum/sub of two FP16 multiplications with accumulation (addition/subtraction) 637 492 431 MHz
Tensor floating-point mode 637 492 431 MHz
Tensor accumulation mode: fp32 637 492 431 MHz
Tensor fixed-point mode 768 655 574 MHz
INT16 complex multiplication mode 768 655 574 MHz
Table 50.  D-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks For specification status, see the Data Sheet Status table
Mode Performance Unit
–1V –2V –3V
Fixed-point 18 x 19 complex multiplication mode 768 655 574 MHz
Fixed-point 18 × 19 FIR systolic mode 768 655 574 MHz
FP32 floating-point complex multiplication 637 492 431 MHz
FP32 floating-point vector dot product 637 492 431 MHz
FP16 floating-point complex multiplication 637 492 431 MHz
FP16 floating-point vector dot product 637 492 431 MHz
Tensor floating-point cascade chain 637 492 431 MHz
Tensor fixed-point cascade chain 768 655 574 MHz
Table 51.  E-Series FPGAs DSP Block Performance Specifications for Single DSP Block For specification status, see the Data Sheet Status table
Mode Performance Unit
–1V –2V, –2E –3V –4S –5S –6S, –6X
Fixed-point 18 × 19 multiplication mode 768 655 574 558 489 408 MHz
Fixed-point 27 × 27 multiplication mode 768 655 574 558 489 408 MHz
Fixed-point 18 × 19 multiplier adder mode 768 655 574 558 489 408 MHz
Fixed-point 18 × 19 multiplier adder summed with 36-bit input mode 768 655 574 558 489 408 MHz
Fixed-point six 9 × 9 multiplier adder mode 768 655 574 558 489 408 MHz
FP32 floating-point multiplication mode 637 492 431 418 367 306 MHz
FP32 floating-point adder or subtract mode 637 492 431 418 367 306 MHz
FP32 floating-point multiplier adder or subtract mode 637 492 431 418 367 306 MHz
FP32 floating-point multiplier accumulate mode 637 492 431 418 367 306 MHz
Addition or subtraction of two FP16 floating-point multiplication mode 637 492 431 418 367 306 MHz
Sum/sub of two FP16 multiplications with FP32 (addition/subtraction) 637 492 431 418 367 306 MHz
Sum/sub of two FP16 multiplications with accumulation (addition/subtraction) 637 492 431 418 367 306 MHz
Tensor floating-point mode 637 492 431 418 367 306 MHz
Tensor accumulation mode: fp32 637 492 431 418 367 306 MHz
Tensor fixed-point mode 768 655 574 558 489 408 MHz
INT16 complex multiplication mode 768 655 574 558 489 408 MHz
Table 52.  E-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks For specification status, see the Data Sheet Status table
Mode Performance Unit
–1V –2V, –2E –3V –4S –5S –6S, –6X
Fixed-point 18 x 19 complex multiplication mode 768 655 574 558 489 408 MHz
Fixed-point 18 × 19 FIR systolic mode 768 655 574 558 489 408 MHz
FP32 floating-point complex multiplication 637 492 431 418 367 306 MHz
FP32 floating-point vector dot product 637 492 431 418 367 306 MHz
FP16 floating-point complex multiplication 637 492 431 418 367 306 MHz
FP16 floating-point vector dot product 637 492 431 418 367 306 MHz
Tensor floating-point cascade chain 637 492 431 418 367 306 MHz
Tensor fixed-point cascade chain 768 655 574 558 489 408 MHz
Level Two Title