Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

HPS Power Supply Operating Conditions

Table 16.  D-Series FPGAs HPS Power Supply Operating Conditions

This table lists the steady-state voltage and current values expected for system-on-a-chip (SoC) devices with Arm*-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions table for the steady-state voltage values expected from the FPGA portion of the SoC devices.

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum Typical Maximum Unit
VCCL_HPS HPS DSU voltage and periphery circuitry power supply SmartVID: –1V, –2V, –3V54 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCL_HPS_CORE0_CORE1 HPS Cortex*-A55 core 0 and core 1 power rail SmartVID: –1V, –2V, –3V54 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCL_HPS_CORE2 HPS Cortex*-A76 core 2 power rail SmartVID: –1V, –2V, –3V54 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCL_HPS_CORE3 HPS Cortex*-A76 core 3 power rail SmartVID: –1V, –2V, –3V54 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCPLLDIG1_HPS HPS PLL1 digital power supply (can be connected to VCCL_HPS) SmartVID: –1V, –2V, –3V54 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCPLLDIG2_HPS HPS PLL2 digital power supply (can be connected to VCCL_HPS) SmartVID: –1V, –2V, –3V54 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
VCCPLL1_HPS HPS PLL1 analog power supply 1.8 V 1.71 1.8 1.89 V
VCCPLL2_HPS HPS PLL2 analog power supply 1.8 V 1.71 1.8 1.89 V
VCCIO_HPS HPS I/O buffers power supply 1.8 V 1.71 1.8 1.89 V
Table 17.  E-Series FPGAs HPS Power Supply Operating Conditions

This table lists the steady-state voltage and current values expected for system-on-a-chip (SoC) devices with Arm*-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions table for the steady-state voltage values expected from the FPGA portion of the SoC devices.

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum Typical Maximum Unit
VCCL_HPS HPS DSU voltage and periphery circuitry power supply SmartVID: –1V, –2V, –2E, –3V55 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V
Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V
Fixed voltage: –6S, –6X (Typical) – 3% 0.75 (Typical) + 3% V
VCCL_HPS_CORE0_CORE1 HPS Cortex*-A55 core 0 and core 1 power rail SmartVID: –1V, –2V, –2E, –3V55 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V
Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V
Fixed voltage: –6S, –6X (Typical) – 3% 0.75 (Typical) + 3% V
VCCL_HPS_CORE2 HPS Cortex*-A76 core 2 power rail SmartVID: –1V, –2V, –2E, –3V55 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V
Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V
Fixed voltage: –6S, –6X (Typical) – 3% 0.75 (Typical) + 3% V
VCCL_HPS_CORE3 HPS Cortex*-A76 core 3 power rail SmartVID: –1V, –2V, –2E, –3V55 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V
Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V
Fixed voltage: –6S, –6X (Typical) – 3% 0.75 (Typical) + 3% V
VCCPLLDIG1_HPS HPS PLL1 digital power supply (can be connected to VCCL_HPS) SmartVID: –1V, –2V, –2E, –3V55 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V
Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V
Fixed voltage: –6S, –6X (Typical) – 3% 0.75 (Typical) + 3% V
VCCPLLDIG2_HPS HPS PLL2 digital power supply (can be connected to VCCL_HPS) SmartVID: –1V, –2V, –2E, –3V55 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4S (Typical) – 3% 0.8 (Typical) + 3% V
Fixed voltage: –5S (Typical) – 3% 0.78 (Typical) + 3% V
Fixed voltage: –6S, –6X (Typical) – 3% 0.75 (Typical) + 3% V
VCCPLL1_HPS HPS PLL1 analog power supply 1.8 V 1.71 1.8 1.89 V
VCCPLL2_HPS HPS PLL2 analog power supply 1.8 V 1.71 1.8 1.89 V
VCCIO_HPS HPS I/O buffers power supply 1.8 V 1.71 1.8 1.89 V
54 The use of Power Management Bus (PMBus*) voltage regulator dedicated to the SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.
55 The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.