Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

HSIO Internal Weak Pull-Up Resistor

All I/O pins in GPIO bank have an option to enable weak pull-up when using 1.0 V, 1.05 V, 1.1 V, 1.2 V, and 1.3 V LVCMOS I/O standards.

Table 22.  HSIO Internal Weak Pull-Up Resistor For specification status, see the Data Sheet Status table
Symbol Description Condition (V) Min Typ Max Unit
RPU Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. VCCIO_PIO = 1.3 ±3% 3 10 30
VCCIO_PIO = 1.2 ±5% 3 10 30
VCCIO_PIO = 1.1 ±5% 3 10 30
VCCIO_PIO = 1.05 ±5% 3 10 30
VCCIO_PIO = 1.0 ±5% 3 10 30