Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 11/25/2024
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Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

AS Configuration Timing

Table 110.  AS Timing Parameters

Intel recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew.

For specification status, see the Data Sheet Status table

Symbol Description Minimum Typical Maximum Unit
Tclk 175 AS_CLK clock period — 6.02 — ns
Tdutycycle AS_CLK duty cycle 45 50 55 %
Tdcsfrs AS_nCSO[3:0] asserted to first AS_CLK edge 8.5176 — — ns
Tdcslst Last AS_CLK edge to AS_nCSO[3:0] deasserted 6.8176 — — ns
Tdo 177 AS_DATA[3:0] output delay –0.6 — 0.6 ns
Text_delay 178 179 180 Total external propagation delay on AS signals — — 13.5 ns
Tdcsb2b Minimum delay of slave select deassertion between two back-to-back transfers 62 — — ns
Skew (AS_CLK – AS_nCSO) Maximum skew tolerance between nCSO and AS_CLK Tsu_ncso – Tdcsfrs < Skew (AS_CLK – AS_nCSO) < AS_CLK/2 + Tdcslst – Tho_ncso 181 ns
Skew (AS_CLK – AS_DATA) Maximum skew tolerance between AS_CLK and AS_DATA –AS_CLK/2 + Tdo(max) + Tsu < Skew (AS_CLK – AS_DATA) < AS_CLK/2 + Tdo(min) – Tho 181 ns
Figure 50. AS Configuration Serial Output Timing Diagram
Figure 51. AS Configuration Serial Input Timing Diagram
175 AS_CLK fMAX has dependency on the maximum board loading. For AS single device configuration or AS using multiple serial flash devices configuration, use the equations in Tdo and Text_delay notes to ensure your board has sufficient timing margin to meet flash setup/hold time specifications and AS timing specifications in this data sheet. For AS using multiple serial flash devices, refer to the Configuration User Guide for the recommended AS_CLK frequency and maximum board loading.
176 AS operating at maximum clock frequency = 166 MHz. The delay is larger when operating at AS clock frequency lower than 166 MHz.
177 Load capacitance for DCLK = 10 pF and AS_DATA = 18 pF. Intel recommends obtaining the Tdo for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPIC simulation. To analyze flash setup time,
  • Tsu = Tclk/2 - Tdo(max) + Tbd_clk – Tbd_data(max)
  • Tho = Tclk/2 + Tdo(min) – Tbd_clk + Tbd_data(min)
178 Text_delay = Tbd_clk + Tco + Tbd_data + Tadd
  • Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.
  • Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the minimum and maximum specification values.
  • Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.
  • Tadd: Propagation delay for active/passive components on AS_DATA interfaces.
179 Text_delay specification is based on AS_CLK = 166 MHz. The value can be larger at lower AS_CLK frequency.
180 Meeting Text_delay timing specifications indicates that the AS_DATA setup/hold timing is met.
181
  • Tsu = Data setup time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
  • Tho = Data hold time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
  • Tdo = AS_DATA[3:0] output delay. Refer to the specification in this table.
  • AS_CLK = AS_CLK clock period.
  • Tsu_ncso = Chip select setup time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
  • Tho_ncso = Chip select hold time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
  • Tdcsfrs = AS_nCSO[3:0] asserted to first AS_CLK edge. Refer to the specification in this table.
  • Tdcslst = Last AS_CLK edge to AS_nCSO[3:0] deasserted. Refer to the specification in this table.
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