Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

AS Configuration Timing

Table 110.  AS Timing Parameters

Intel recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew.

For specification status, see the Data Sheet Status table

Symbol Description Minimum Typical Maximum Unit
Tclk 175 AS_CLK clock period 6.02 ns
Tdutycycle AS_CLK duty cycle 45 50 55 %
Tdcsfrs AS_nCSO[3:0] asserted to first AS_CLK edge 8.5176 ns
Tdcslst Last AS_CLK edge to AS_nCSO[3:0] deasserted 6.8176 ns
Tdo 177 AS_DATA[3:0] output delay –0.6 0.6 ns
Text_delay 178 179 180 Total external propagation delay on AS signals 0 13.5 ns
Tdcsb2b Minimum delay of slave select deassertion between two back-to-back transfers 62 ns
Skew (AS_CLKAS_nCSO) Maximum skew tolerance between nCSO and AS_CLK Tsu_ncso – Tdcsfrs < Skew (AS_CLKAS_nCSO) < AS_CLK/2 + Tdcslst – Tho_ncso 181 ns
Skew (AS_CLKAS_DATA) Maximum skew tolerance between AS_CLK and AS_DATA AS_CLK/2 + Tdo(max) + Tsu < Skew (AS_CLKAS_DATA) < AS_CLK/2 + Tdo(min) – Tho 181 ns
Figure 50. AS Configuration Serial Output Timing Diagram
Figure 51. AS Configuration Serial Input Timing Diagram
175 AS_CLK fMAX has dependency on the maximum board loading. For AS single device configuration or AS using multiple serial flash devices configuration, use the equations in Tdo and Text_delay notes to ensure your board has sufficient timing margin to meet flash setup/hold time specifications and AS timing specifications in this data sheet. For AS using multiple serial flash devices, refer to the Configuration User Guide for the recommended AS_CLK frequency and maximum board loading.
176 AS operating at maximum clock frequency = 166 MHz. The delay is larger when operating at AS clock frequency lower than 166 MHz.
177 Load capacitance for DCLK = 10 pF and AS_DATA = 18 pF. Intel recommends obtaining the Tdo for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPIC simulation. To analyze flash setup time,
  • Tsu = Tclk/2 - Tdo(max) + Tbd_clk – Tbd_data(max)
  • Tho = Tclk/2 + Tdo(min) – Tbd_clk + Tbd_data(min)
178 Text_delay = Tbd_clk + Tco + Tbd_data + Tadd
  • Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.
  • Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the minimum and maximum specification values.
  • Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.
  • Tadd: Propagation delay for active/passive components on AS_DATA interfaces.
179 Text_delay specification is based on AS_CLK = 166 MHz. The value can be larger at lower AS_CLK frequency.
180 Meeting Text_delay timing specifications indicates that the AS_DATA setup/hold timing is met.
181
  • Tsu = Data setup time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
  • Tho = Data hold time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
  • Tdo = AS_DATA[3:0] output delay. Refer to the specification in this table.
  • AS_CLK = AS_CLK clock period.
  • Tsu_ncso = Chip select setup time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
  • Tho_ncso = Chip select hold time required by the quad SPI flash. Refer to your quad SPI flash datasheet.
  • Tdcsfrs = AS_nCSO[3:0] asserted to first AS_CLK edge. Refer to the specification in this table.
  • Tdcslst = Last AS_CLK edge to AS_nCSO[3:0] deasserted. Refer to the specification in this table.