Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

HSIO Differential POD I/O Standards Specifications

Table 36.  HSIO Differential POD I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) VILdiff(DC) (V) VIHdiff(DC) (V) VILdiff(AC) (V) VIHdiff(AC) (V) VIX(AC) (%)68
Min Typ Max Max Min Max Min Max
POD1269 1.164 1.2 1.236 –0.11 0.11 –0.14 0.14 25
POD1169 1.067 1.1 1.133 –0.11 0.11 –0.14 0.14 25
68 Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings.
69 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-bank is operating in any of the following modes. Else, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.
  • PHYLITE mode
  • GPIO mode