Agilex™ 5 FPGAs and SoCs Device Data Sheet

Download PDF
ID 813918
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet

Document Version Changes
2024.11.25
  • Updated the minimum value of Text_delay symbol in the AS Timing Parameters table.
  • Update the maximum data rate for LVDS SERDES Receiver specifications in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and D-Series and E-Series Device Group B FPGAs LVDS SERDES Specifications tables.
  • Minor update on the description in the HVIO Hysteresis Specifications for Schmitt Trigger Input table.
  • Updated the maximum frequency of DDR4 SDRAM Memory Standards in the D-Series FPGAs Memory Standards Supported and E-Series Device Group B FPGAs Memory Standards Supported tables.
  • Minor update in the footnote for the Voltage Sensor Specifications table.
  • Updated the fHSDR data rate (without DPA) in SERDES factor J = 4 and 8 specifications in the D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications and D-Series and E-Series Device Group B FPGAs LVDS SERDES Specifications tables.
  • Updated the clause used to IEEE 802.3by for 25GAUI-C2C/C2M in the Electrical Compliance List table.
  • Updated the Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] (Th) specifications in the HPS USB UPLI Timing Characteristics table.
2024.08.05
  • Added note on 100 ohm for VCCIO_PIO in HSIO OCT Without Calibration Resistance Tolerance Specifications table.
  • Updated the minimum timing parameters for tADSU and tAVSU symbols in Avalon Streaming Timing Parameters for x8 and x16 Configurations table.
  • Updated the specifications in HVIO I/O Pin Leakage Current table.
  • Updated the specifications in HVIO Internal Weak Pull-Up and Pull Down Resistor Value table.
  • Updated the specifications in D-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications and E-Series FPGAs MIPI D-PHY Low-Power I/O Standards Specifications tables.
  • Updated the specifications in the -E6S, -I6S, -E6X and -I6X speed grade in Programmable IOE Delay Specifications table.
  • Updated the LPDDR5 SDRAM Memory Standard paramaters in E-Series Device Group B FPGAs Memory Standards Supported table.
  • Added footnote for Receiver DPA mode with J-factor 4 and 8 for all speed grade at maximum corner data rates in the following tables:
    • D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications
    • E-Series Device Group B FPGAs LVDS SERDES Specifications
  • Updated the Typical values in the HPS Programmable I/O Delay (Output Path) and HPS Programmable I/O Delay (Input Path) tables.
  • Updated tINCCJ specifications to ±750 ps in I/O PLL Specifications table.
  • Added CML and HSCL as the supported I/O standards in GTS Transceiver and System PLL Reference Clock Input Specifications table.
2024.04.01 Initial release.
2023.08.11
  • Updated the D-Series FPGAs Absolute Maximum Ratings table.
    • Updated the symbol from VCCLHPS_ADC_SDM to VCCL_ADC_SDM and updated description.
    • Added VCCIO_PIO specifications for VCCIO_PIO = 1.0 V.
    • Updated VI specifications and footnote.
    • Updated IOUT specifications and added footnote.
  • Updated the E-Series FPGAs Absolute Maximum Ratings table.
    • Updated –6L to –6X speed grade.
    • Updated the symbol from VCCLHPS_ADC_SDM to VCCL_ADC_SDM and updated description.
    • Added VCCIO_PIO specifications for VCCIO_PIO = 1.0 V.
    • Updated VI specifications and footnote.
    • Updated IOUT specifications and added footnote.
  • Updated the description in the Maximum Allowed Overshoot and Undershoot Voltage section and added the following tables:
    • Maximum Allowed Overshoot During Transitions for 1.0 V I/O in HSIO Bank
    • Maximum Allowed Overshoot During Transitions for 1.3 V I/O in HSIO Bank
  • Updated the D-Series FPGAs Recommended Operating Conditions table.
    • Updated VCCIO_PIO_SDM specifications.
    • Updated the symbol from VCCLHPS_ADC_SDM to VCCL_ADC_SDM and updated description.
    • Updated VCCIO_PIO specifications and footnote.
    • Updated VI specifications and footnote.
    • Added VO specifications for VCCIO_PIO = 1.0 V.
    • Updated tRAMP footnote.
  • Updated the E-Series FPGAs Recommended Operating Conditions table.
    • Updated –6L to –6X speed grade.
    • Updated VCCH_SDM, VCCIO_PIO_SDM, and VCC_IO_SDM specifications.
    • Updated the symbol from VCCLHPS_ADC_SDM to VCCL_ADC_SDM and updated description.
    • Updated VCCIO_PIO specifications and footnote.
    • Updated VI specifications and footnote.
    • Added VO specifications for VCCIO_PIO = 1.0 V.
    • Updated tRAMP footnote.
  • Added footnote to maximum value column in the D-Series FPGAs GTS Transceiver Power Supply Operating Conditions table.
  • Updated the E-Series FPGAs GTS Transceiver Power Supply Operating Conditions table.
    • Added footnote to maximum value column.
    • Updated –6L to –6X speed grade.
  • Updated the HSIO OCT Calibration Accuracy Specifications table.
    • Removed 50-Ω RS specification.
    • Added footnote to RS and RT.
    • Removed DPHY11 I/O standards support.
  • Updated the HSIO OCT Without Calibration Resistance Tolerance Specifications table.
    • Added 34-Ω and 40-Ω RS specifications for 1.0 V LVCMOS and 1.3 V LVCMOS I/O standards.
    • Added footnote to RS and RT.
  • Added specifications for VCCIO_PIO = 1.0 ±5% and VCCIO_PIO = 1.3 ±5% in the HSIO Internal Weak Pull-Up Resistor table.
  • Updated II and IOZ specifications for VI = 0 V to VCCIO_HVIO = 2.5 V in the HVIO I/O Pin Leakage Current table.
  • Updated CIO specification in the HVIO Pin Capacitance table.
  • Updated VHYS specification for VCCIO_HVIO = 3.3 V in the HVIO Hysteresis Specifications for Schmitt Trigger Input table.
  • Added specifications for 1.0 V LVCMOS and 1.3 V LVCMOS I/O standards in the HSIO Single-Ended I/O Standards Specifications table.
  • Updated POD11 and POD12 specifications in the HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications table.
  • Updated LVSTL11, LVSTL105, and LVSTL700 specifications in the HSIO Single-Ended LVSTL I/O Standards Specifications table.
  • Added footnote to SSTL-12, HSTL-12, and HSUL-12 in the HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications table.
  • Updated POD11 and POD12 specifications in the HSIO Differential POD I/O Standards Specifications table.
  • Updated LVSTL11, LVSTL105, and LVSTL700 specifications in the HSIO Differential LVSTL I/O Standards Specifications table.
  • Updated fIN specifications in the D-Series FPGAs I/O PLL Specifications table.
  • Updated the E-Series FPGAs I/O PLL Specifications table.
    • Updated fIN specifications.
    • Updated –6L to –6X speed grade.
  • Updated Fixed-point complex multiplication mode to Fixed-point 18 x 19 complex multiplication mode in the D-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks table.
  • Updated –6L to –6X speed grade in the E-Series FPGAs DSP Block Performance Specifications for Single DSP Block table.
  • Updated the E-Series FPGAs DSP Block Performance Specifications for Multiple DSP Blocks table.
    • Updated –6L to –6X speed grade.
    • Updated Fixed-point complex multiplication mode to Fixed-point 18 x 19 complex multiplication mode.
  • Updated –6L to –6X speed grade in the E-Series FPGAs Memory Block Performance Specifications table.
  • Updated the Voltage Sensor Specifications table.
    • Added external reference voltage specifications.
    • Updated footnote to voltage sensor accuracy, Vin.
  • Split the LVDS SERDES Specifications table into the following tables and updated specifications:
    • D-Series and E-Series Device Group A FPGAs LVDS SERDES Specifications
    • E-Series Device Group B FPGAs LVDS SERDES Specifications
  • Removed TPP-JITTER-TOLERANCE specifications in the System PLL Reference Clock (Using HVIO) Specifications table.
  • Updated the Electrical Compliance List table.
    • Updated specification for IEEE 802.3by 111/110 and CPRI V7.0.
    • Added footnote to PCIe BASE 4.0 / PIPE 4.4.1 specification.
    • Updated specification/clause and protocol for USB.
  • Removed the following RMII content:
    • Reduced Media Independent Interface (RMII) Clock Timing Requirements table
    • RMII TX Timing Requirements table
    • RMII TX Timing Diagram
    • RMII RX Timing Requirements table
    • RMII RX Timing Diagram
  • Removed ONFI 3.x, INFI 4.x, NV-DDR2, and NV-DDR3 in the table description of the following tables:
    • HPS NAND SDR Timing Requirements
    • HPS NAND DDR Timing Requirements
  • Updated tJCP, tJCH, tJCL, tJPSU (TMS), tJPH, tJPCO, tJPZX, and tJPXZ specifications in the JTAG Timing Parameters and Values table.
  • Updated tACLKH, tACLKL, tACLKP, tADSU, tADH, and tAVSU specifications in the Avalon Streaming Timing Parameters for ×8 and ×16 Configurations table.
  • Updated the Programmable IOE Delay Specifications table.
    • Added specifications for Output Enable Delay Chain (OUTPUT_EENABLE_DELAY_CHAIN).
    • Updated –6L to –6X speed grade.
2023.03.27 Initial release.
Level Two Title