Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

HVIO I/O Pin Leakage Current

Table 23.  HVIO I/O Pin Leakage Current For specification status, see the Data Sheet Status table
Symbol Description Condition Min Max Unit
II Input pin VI = 0 V to VCCIO_HVIO (MAX) -10 10 μA
IOZ Tri-stated I/O pin VI = 0 V to VCCIO_HVIO (MAX) -10 10 μA