Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

HPS Clock Performance

Table 74.  D-Series SoC Maximum HPS Clock Frequencies For specification status, see the Data Sheet Status table
Performance VCCL_HPS (V)140 Cortex-A55 Core Frequency (MHz) Cortex-A76 Core Frequency (MHz) DSU (DynamIQ Shared Unit) Frequency (MHz) (mpu_free_clk) L3 Frequency (MHz) (l3_main_free_clk) DDR4/LPDDR4/DDR5/LPDDR5 Clock (MHz)
–1 speed grade SmartVID 1,500 1,800 1,200 400 Refer to the Memory Standards Supported table.
–2 speed grade SmartVID 1,333 1,600 1,066 400
–3 speed grade SmartVID 1,250 1,400 933 400
Table 75.  E-Series SoC Maximum HPS Clock Frequencies For specification status, see the Data Sheet Status table
Performance VCCL_HPS (V)141 Cortex-A55 Core Frequency (MHz) Cortex-A76 Core Frequency (MHz) DSU (DynamIQ Shared Unit) Frequency (MHz) (mpu_free_clk) L3 Frequency (MHz) (l3_main_free_clk) DDR4/LPDDR4/DDR5/LPDDR5 Clock (MHz)
–1 speed grade SmartVID 1,500 1,800 1,200 400 Refer to the Memory Standards Supported table.
–2 speed grade SmartVID 1,333 1,600 1,066 400
–3 speed grade SmartVID 1,250 1,400 933 400
–4 speed grade Fixed: 0.8 1,250 1,400 933 400
–5 speed grade Fixed: 0.78 800 800 533 400
–6 speed grade Fixed: 0.75 800 800 533 400
140 VCCL_HPS refers to VCCL_HPS_CORE0_CORE1 for HPS Cortex-A55 core 0 and core 1 power rail, VCCL_HPS_CORE2 for HPS Cortex-A76 core 2 power rail, and VCCL_HPS_CORE3 for HPS Cortex-A76 core 3 power rail.
141 VCCL_HPS refers to VCCL_HPS_CORE0_CORE1 for HPS Cortex-A55 core 0 and core 1 power rail, VCCL_HPS_CORE2 for HPS Cortex-A76 core 2 power rail, and VCCL_HPS_CORE3 for HPS Cortex-A76 core 3 power rail.