Agilex™ 5 FPGAs and SoCs Device Data Sheet

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ID 813918
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 5 FPGAs and SoCs Device Data Sheet
Agilex™ 5 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 5 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS and SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up and Weak Pull-Down Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS and SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, POD, and LVSTL I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 5 FPGAs and SoCs Device Data Sheet

HPS Clock Performance

Table 74.  D-Series SoC Maximum HPS Clock Frequencies For specification status, see the Data Sheet Status table
Performance VCCL_HPS (V)140 Cortex-A55 Core Frequency (MHz) Cortex-A76 Core Frequency (MHz) DSU (DynamIQ Shared Unit) Frequency (MHz) (mpu_free_clk) L3 Frequency (MHz) (l3_main_free_clk) DDR4/LPDDR4/DDR5/LPDDR5 Clock (MHz)
–1 speed grade SmartVID 1,500 1,800 1,200 400 Refer to the Memory Standards Supported table.
–2 speed grade SmartVID 1,333 1,600 1,066 400
–3 speed grade SmartVID 1,250 1,400 933 400
Table 75.  E-Series SoC Maximum HPS Clock Frequencies For specification status, see the Data Sheet Status table
Performance VCCL_HPS (V)141 Cortex-A55 Core Frequency (MHz) Cortex-A76 Core Frequency (MHz) DSU (DynamIQ Shared Unit) Frequency (MHz) (mpu_free_clk) L3 Frequency (MHz) (l3_main_free_clk) DDR4/LPDDR4/DDR5/LPDDR5 Clock (MHz)
–1 speed grade SmartVID 1,500 1,800 1,200 400 Refer to the Memory Standards Supported table.
–2 speed grade SmartVID 1,333 1,600 1,066 400
–3 speed grade SmartVID 1,250 1,400 933 400
–4 speed grade Fixed: 0.8 1,250 1,400 933 400
–5 speed grade Fixed: 0.78 800 800 533 400
–6 speed grade Fixed: 0.75 800 800 533 400
Related Information
140 VCCL_HPS refers to VCCL_HPS_CORE0_CORE1 for HPS Cortex-A55 core 0 and core 1 power rail, VCCL_HPS_CORE2 for HPS Cortex-A76 core 2 power rail, and VCCL_HPS_CORE3 for HPS Cortex-A76 core 3 power rail.
141 VCCL_HPS refers to VCCL_HPS_CORE0_CORE1 for HPS Cortex-A55 core 0 and core 1 power rail, VCCL_HPS_CORE2 for HPS Cortex-A76 core 2 power rail, and VCCL_HPS_CORE3 for HPS Cortex-A76 core 3 power rail.
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