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Ixiasoft
HSIO Single-Ended I/O Standards Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
HSIO Single-Ended LVSTL I/O Standards Specifications
HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications
HSIO Differential POD I/O Standards Specifications
HSIO Differential LVSTL I/O Standards Specifications
HSIO Differential I/O Standards Specifications
MIPI D-PHY I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/eMMC Timing Characteristics
HPS USB 2.0 Timing Characteristics
HPS USB 3.1 Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS I3C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: xwn1662081102983
Ixiasoft
Recommended Operating Conditions
Symbol | Description | Condition | Minimum26 | Typical | Maximum26 | Unit |
---|---|---|---|---|---|---|
VCC | Core voltage supply | SmartVID27 : –1V, –2V, –3V | (Typical) – 3% | 0.70 – 0.9028 | (Typical) + 3% | V |
VCCP | Periphery supply voltage for the I/O banks | SmartVID27: –1V, –2V, –3V | (Typical) – 3% | 0.70 – 0.9028 | (Typical) + 3% | V |
VCCH_SDM | SDM block AIB I/O supply voltage sense | — | 0.975 | 1 | 1.025 | V |
VCCPT 29 | Power supply for I/O, DTS, SDM, and system PLL | — | 1.746 | 1.8 | 1.854 | V |
VCCRCORE | Power supply for programmable power technology | — | 1.14 | 1.2 | 1.26 | V |
VCCBAT | Battery back-up power supply (for design security volatile key register) | — | 1 | 1 – 1.80 | 1.8 | V |
IBAT | Battery back-up power supply (for design security volatile key register) | VCCBAT = 1.2 V | — | — | 200 | nA |
VCCIO_PIO_SDM 30 | SDM block I/O supply voltage sense of bank 3A | 1.2 V | 1.164 | 1.2 | 1.236 | V |
VCC_IO_SDM | I/O digital supply voltage sense in SDM block | SmartVID27: –1V, –2V, –3V | (Typical) – 3% | 0.70 – 0.9028 | (Typical) + 3% | V |
VCCIO_SDM | SDM block configuration pins power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCL_ADC_SDM | Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices | SmartVID27: –1V, –2V, –3V | (Typical) – 3% | 0.70 – 0.9028 | (Typical) + 3% | V |
VCCL_SDM | SDM digital power supply | — | 0.776 | 0.8 | 0.824 | V |
VCCPLLDIG_SDM | SDM block PLL digital power supply | — | 0.776 | 0.8 | 0.824 | V |
VCCPLL_SDM | SDM block PLL analog power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCFUSEWR_SDM | Fuse block writing power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCADC | ADC voltage sensor power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCIO_PIO | HSIO bank power supply | 1.0 V | 0.95 | 1 | 1.05 | V |
1.05 V31 | 1.0185 | 1.05 | 1.0815 | V | ||
1.1 V31 | 1.067 | 1.1 | 1.133 | V | ||
1.2 V31 | 1.164 | 1.2 | 1.236 | V | ||
1.3 V | 1.261 | 1.3 | 1.339 | V | ||
VCCIO_HVIO | HVIO bank power supply | 3.3 V | 3.201 | 3.3 | 3.399 | V |
2.5 V | 2.425 | 2.5 | 2.575 | V | ||
1.8 V | 1.746 | 1.8 | 1.854 | V | ||
VCCPT_HVIO | Supply voltage for 1.8 V I/O | — | 1.746 | 1.8 | 1.854 | V |
VI 32 | DC input voltage | VCCIO_PIO = 1.0 V33 | –0.3000 | — | VCCIO_PIO + 0.25 | V |
VCCIO_PIO = 1.05 V34 33 | –0.3000 | — | VCCIO_PIO + 0.25 | V | ||
VCCIO_PIO = 1.1 V34 33 | –0.3000 | — | VCCIO_PIO + 0.25 | V | ||
VCCIO_PIO = 1.2 V34 33 | –0.3000 | — | VCCIO_PIO + 0.25 | V | ||
VCCIO_PIO = 1.3 V34 33 | –0.3000 | — | VCCIO_PIO + 0.25 | V | ||
VCCIO_SDM = 1.8 V | –0.3000 | — | VCCIO_SDM + 0.3 | V | ||
VCCIO_HPS = 1.8 V | –0.3000 | — | VCCIO_HPS + 0.3 | V | ||
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V | –0.3000 | — | VCCIO_HVIO + 0.3 | V | ||
VO | Output voltage | VCCIO_PIO = 1.0 V, 1.05 V, 1.1 V, 1.2 V, 1.3 V | 0 | — | VCCIO_PIO | V |
VCCIO_SDM = 1.8 V | 0 | — | VCCIO_SDM | V | ||
VCCIO_HPS = 1.8 V | 0 | — | VCCIO_HPS | V | ||
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V | 0 | — | VCCIO_HVIO | V | ||
TJ | Operating junction temperature | Extended | 0 | — | 10035 | °C |
Industrial | –40 | — | 10035 | °C | ||
tRAMP 36 37 | Power supply ramp time | Standard POR | 200 μs | — | 100 ms | — |
Symbol | Description | Condition | Minimum38 | Typical | Maximum38 | Unit |
---|---|---|---|---|---|---|
VCC | Core voltage supply | SmartVID39 : –1V, –2V, –2E, –3V | (Typical) – 3% | 0.70 – 0.9040 | (Typical) + 3% | V |
Fixed voltage: –4S | 0.776 | 0.8 | 0.824 | V | ||
Fixed voltage: –5S | 0.756 | 0.78 | 0.803 | V | ||
Fixed voltage: –6S, –6X | 0.7275 | 0.75 | 0.7725 | V | ||
VCCP | Periphery supply voltage for the I/O banks | SmartVID39: –1V, –2V, –2E, –3V | (Typical) – 3% | 0.70 – 0.9040 | (Typical) + 3% | V |
Fixed voltage: –4S | 0.776 | 0.8 | 0.824 | V | ||
Fixed voltage: –5S | 0.756 | 0.78 | 0.803 | V | ||
Fixed voltage: –6S, –6X | 0.7275 | 0.75 | 0.7725 | V | ||
VCCH_SDM | SDM block AIB I/O supply voltage sense | SmartVID39: –1V, –2V, –2E, –3V | 0.776 | 0.8 | 0.824 | V |
Without transceiver: –4S | 0.776 | 0.8 | 0.824 | V | ||
Without transceiver: –5S | 0.756 | 0.78 | 0.803 | V | ||
Without transceiver: –6S, –6X | 0.7275 | 0.75 | 0.7725 | V | ||
With transceiver | 0.975 | 1 | 1.025 | V | ||
VCCPT 41 | Power supply for I/O, DTS, SDM, and system PLL | — | 1.746 | 1.8 | 1.854 | V |
VCCRCORE | Power supply for programmable power technology | — | 1.14 | 1.2 | 1.26 | V |
VCCBAT | Battery back-up power supply (for design security volatile key register) | — | 1 | 1 – 1.80 | 1.8 | V |
IBAT | Battery back-up power supply (For design security volatile key register) | VCCBAT = 1.2 V | — | — | 200 | nA |
VCCIO_PIO_SDM 42 | SDM block I/O supply voltage sense of bank 3A | 1.2 V | 1.164 | 1.2 | 1.236 | V |
VCC_IO_SDM | I/O digital supply voltage sense in SDM block | SmartVID39: –1V, –2V, –2E, –3V | (Typical) – 3% | 0.70 – 0.9040 | (Typical) + 3% | V |
Fixed voltage: –4S | 0.776 | 0.8 | 0.824 | V | ||
Fixed voltage: –5S | 0.756 | 0.78 | 0.803 | V | ||
Fixed voltage: –6S, –6X | 0.7275 | 0.75 | 0.7725 | V | ||
VCCIO_SDM | SDM block configuration pins power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCL_ADC_SDM | Periphery digital supply voltage sense to ADC, senses HPS digital supply on HPS devices, core supply on non-HPS devices | SmartVID39: –1V, –2V, –2E, –3V | (Typical) – 3% | 0.70 – 0.9040 | (Typical) + 3% | V |
Fixed voltage: –4S | 0.776 | 0.8 | 0.824 | V | ||
Fixed voltage: –5S | 0.756 | 0.78 | 0.803 | V | ||
Fixed voltage: –6S, –6X | 0.7275 | 0.75 | 0.7725 | V | ||
VCCL_SDM | SDM digital power supply | SmartVID39: –1V, –2V, –2E, –3V | 0.776 | 0.8 | 0.824 | V |
Fixed voltage: –4S | 0.776 | 0.8 | 0.824 | V | ||
Fixed voltage: –5S | 0.756 | 0.78 | 0.803 | V | ||
Fixed voltage: –6S, –6X | 0.7275 | 0.75 | 0.7725 | V | ||
VCCPLLDIG_SDM | SDM block PLL digital power supply | SmartVID39: –1V, –2V, –2E, –3V | 0.776 | 0.8 | 0.824 | V |
Fixed voltage: –4S | 0.776 | 0.8 | 0.824 | V | ||
Fixed voltage: –5S | 0.756 | 0.78 | 0.803 | V | ||
Fixed voltage: –6S, –6X | 0.7275 | 0.75 | 0.7725 | V | ||
VCCPLL_SDM | SDM block PLL analog power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCFUSEWR_SDM | Fuse block writing power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCADC | ADC voltage sensor power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCIO_PIO | HSIO bank power supply | 1.0 V | 0.95 | 1 | 1.05 | V |
1.05 V43 | 1.0185 | 1.05 | 1.0815 | V | ||
1.1 V43 | 1.067 | 1.1 | 1.133 | V | ||
1.2 V43 | 1.164 | 1.2 | 1.236 | V | ||
1.3 V | 1.261 | 1.3 | 1.339 | V | ||
VCCIO_HVIO | HVIO bank power supply | 3.3 V | 3.201 | 3.3 | 3.399 | V |
2.5 V | 2.425 | 2.5 | 2.575 | V | ||
1.8 V | 1.746 | 1.8 | 1.854 | V | ||
VCCPT_HVIO | Supply voltage for 1.8 V I/O | — | 1.746 | 1.8 | 1.854 | V |
VI 44 | DC input voltage | VCCIO_PIO = 1.0 V45 | –0.3000 | — | VCCIO_PIO + 0.25 | V |
VCCIO_PIO = 1.05 V46 45 | –0.3000 | — | VCCIO_PIO + 0.25 | V | ||
VCCIO_PIO = 1.1 V46 45 | –0.3000 | — | VCCIO_PIO + 0.25 | V | ||
VCCIO_PIO = 1.2 V46 45 | –0.3000 | — | VCCIO_PIO + 0.25 | V | ||
VCCIO_PIO = 1.3 V46 45 | –0.3000 | — | VCCIO_PIO + 0.25 | V | ||
VCCIO_SDM = 1.8 V | –0.3000 | — | VCCIO_SDM + 0.3 | V | ||
VCCIO_HPS = 1.8 V | –0.3000 | — | VCCIO_HPS + 0.3 | V | ||
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V | –0.3000 | — | VCCIO_HVIO + 0.3 | V | ||
VO | Output voltage | VCCIO_PIO = 1.0 V, 1.05 V, 1.1 V, 1.2 V, 1.3 V | 0 | — | VCCIO_PIO | V |
VCCIO_SDM = 1.8 V | 0 | — | VCCIO_SDM | V | ||
VCCIO_HPS = 1.8 V | 0 | — | VCCIO_HPS | V | ||
VCCIO_HVIO = 1.8 V, 2.5 V, 3.3 V | 0 | — | VCCIO_HVIO | V | ||
TJ | Operating junction temperature | Extended | 0 | — | 10047 | °C |
Industrial | –40 | — | 10047 | °C | ||
tRAMP 48 49 | Power supply ramp time | Standard POR | 200 μs | — | 100 ms | — |
Related Information
26 This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise.
27 The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.
28 The typical value is based on the SmartVID programmed value.
29 Must use a tolerance of ±3% when sharing with VCCIO_HVIO. A tolerance of ±5% is only allowed when VCCPT is not shared with other rails.
30 Must be supplied at 1.2 V when using Avalon® Streaming ×16 configuration schemes. For more information, please refer to the Agilex® 5 Device Family Pin Connection Guidelines.
31 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-bank is operating in any of the following modes:
- LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, 1.2 V True Differential Signaling input standard
- PHYLITE mode
- GPIO mode
32 This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.
33 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI(DC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V.
34 Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.
35 When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device lifetime of 11.4 years.
36 tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies. The ramp time applies to both the ramp-up and ramp-down of the power rails.
37 To support AS fast mode, all power supplies to the device must be fully ramped-up within 10 ms to the recommended operating conditions.
38 This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise.
39 The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.
40 The typical value is based on the SmartVID programmed value.
41 Must use a tolerance of ±3% when sharing with VCCIO_HVIO. A tolerance of ±5% is only allowed when VCCPT is not shared with other rails.
42 Must be supplied at 1.2 V when using Avalon® Streaming ×16 configuration schemes. For more information, please refer to the Agilex® 5 Device Family Pin Connection Guidelines.
43 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-bank is operating in any of the following modes:
- LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, 1.2 V True Differential Signaling input standard
- PHYLITE mode
- GPIO mode
44 This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.
45 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI(DC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V.
46 Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.
47 When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device lifetime of 11.4 years.
48 tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies. The ramp time applies to both the ramp-up and ramp-down of the power rails.
49 To support AS fast mode, all power supplies to the device must be fully ramped-up within 10 ms to the recommended operating conditions.