Visible to Intel only — GUID: gjr1662081204102
Ixiasoft
Visible to Intel only — GUID: gjr1662081204102
Ixiasoft
LVDS SERDES Specifications
Parameter | Symbol | Condition | –1 Speed Grade | –2 Speed Grade | –3 Speed Grade | Unit | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
Clock frequency | fHSCLK_in (input clock frequency) True Differential Signaling I/O Standards | Clock boost factor W = 1 to 40103 | 10 | — | 800 | 10 | — | 800 | 10 | — | 625 | MHz |
fHSCLK_in (input clock frequency) SLVS400 I/O Standards | Clock boost factor W = 1 to 40103 | 10 | — | 435.5 | 10 | — | 435.5 | 10 | — | 435.5 | MHz | |
fHSCLK_in (input clock frequency) Single-Ended I/O Standards | Clock boost factor W = 1 to 40103 | 10 | — | 625 | 10 | — | 625 | 10 | — | 525 | MHz | |
fHSCLK_OUT (output clock frequency) True Differential Signaling I/O Standards | — | — | — | 800 | — | — | 800 | — | — | 625 | MHz | |
Transmitter | True Differential Signaling I/O Standards - fHSDR (data rate)104 | SERDES factor J = 4 and 8105 106 107 | 600 | — | 1,600 | 600 | — | 1,600 | 600 | — | 1,250 | Mbps |
SERDES factor J = 2, uses DDR registers | 150 | — | 840108 | 150 | — | 108 | 150 | — | 108 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 150 | — | 420108 | 150 | — | 108 | 150 | — | 108 | Mbps | ||
tx Jitter - True Differential Signaling I/O Standards | Total jitter for data rate, 600 Mbps – 1.6 Gbps | ≤1,600 Mbps: 160 ≤1,434 Mbps: 200 ≤1,250 Mbps: 250 ≤1,000 Mbps: 300 ≤800 Mbps: 320 600 Mbps: 340 |
≤1,600 Mbps: 160 ≤1,434 Mbps: 200 ≤1,250 Mbps: 250 ≤1,000 Mbps: 300 ≤800 Mbps: 320 600 Mbps: 340 |
≤1,250 Mbps: 250 ≤1,000 Mbps: 300 ≤800 Mbps: 320 600 Mbps: 340 |
ps | |||||||
tDUTY 109 | TX output clock duty cycle for True Differential Signaling I/O Standards | 45 | 50 | 55 | 45 | 50 | 55 | 45 | 50 | 55 | % | |
tRISE and tFALL 106 110 | True Differential Signaling I/O Standards | — | — | 160 | — | — | 160 | — | — | 200 | ps | |
TCCS 104 109 | True Differential Signaling I/O Standards | — | — | 330 | — | — | 330 | — | — | 330 | ps | |
Receiver | True Differential Signaling I/O Standards - fHSDRDPA (data rate) | SERDES factor J = 4 and 8105 106 107 | 600 | — | 1600111 | 600 | — | 1600111 | 600 | — | 1250111 | Mbps |
SLVS400 I/O Standards - fHSDRDPA (data rate) | SERDES factor J = 4 and 8105 106 107 | 600 | — | 891 | 600 | — | 891 | 600 | — | 891 | Mbps | |
fHSDR (data rate) (without DPA)104 | SERDES factor J = 4 and 8105 106 107 | 107 | — | 112 | 107 | — | 112 | 107 | — | 112 | Mbps | |
SERDES factor J = 2, uses DDR registers | 107 | — | 108 | 107 | — | 108 | 107 | — | 108 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 107 | — | 108 | 107 | — | 108 | 107 | — | 108 | Mbps | ||
DPA (FIFO mode) | DPA run length | — | — | — | ≤10,000 | — | — | ≤10,000 | — | — | ≤10,000 | UI |
DPA (soft CDR mode) | DPA run length | SGMII/GbE protocol | — | — | 5 | — | — | 5 | — | — | 5 | UI |
All other protocols | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | ||
Soft CDR mode | Soft-CDR ppm tolerance | — | –300 | — | 300 | –300 | — | 300 | –300 | — | 300 | ppm |
Non DPA mode | Sampling window | — | — | — | 330 | — | — | 330 | — | — | 330 | ps |
Parameter | Symbol | Condition | –4 Speed Grade | –5 Speed Grade | –6 Speed Grade | Unit | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
Clock frequency | fHSCLK_in (input clock frequency) True Differential Signaling I/O Standards | Clock boost factor W = 1 to 40113 | 10 | — | 625 | 10 | — | 625 | 10 | — | 500 | MHz |
fHSCLK_in (input clock frequency) SLVS400 I/O Standards | Clock boost factor W = 1 to 40113 | 10 | — | 435.5 | 10 | — | 435.5 | 10 | — | 435.5 | MHz | |
fHSCLK_in (input clock frequency) Single-Ended I/O Standards | Clock boost factor W = 1 to 40113 | 10 | — | 625 | 10 | — | 625 | 10 | — | 525 | MHz | |
fHSCLK_OUT (output clock frequency) True Differential Signaling I/O Standards | — | — | — | 625 | — | — | 625 | — | — | 500 | MHz | |
Transmitter | True Differential Signaling I/O Standards - fHSDR (data rate)114 | SERDES factor J = 4 and 8115 116 117 | 600 | — | 1,250 | 600 | — | 1,250 | 600 | — | 1,000 | Mbps |
SERDES factor J = 2, uses DDR registers | 150 | — | 840118 | 150 | — | 118 | 150 | — | 118 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 150 | — | 420118 | 150 | — | 118 | 150 | — | 118 | Mbps | ||
tx Jitter - True Differential Signaling I/O Standards | Total jitter for data rate, 600 Mbps – 1.25 Gbps | ≤1,250 Mbps: 250 ≤1,000 Mbps: 300 ≤800 Mbps: 320 600 Mbps: 340 |
≤1,250 Mbps: 250 ≤1,000 Mbps: 300 ≤800 Mbps: 320 600 Mbps: 340 |
≤1,000 Mbps: 300 ≤800 Mbps: 320 600 Mbps: 340 |
ps | |||||||
tDUTY 119 | TX output clock duty cycle for True Differential Signaling I/O Standards | 45 | 50 | 55 | 45 | 50 | 55 | 45 | 50 | 55 | % | |
tRISE and tFALL 116 120 | True Differential Signaling I/O Standards | — | — | 160 | — | — | 160 | — | — | 200 | ps | |
TCCS 114 119 | True Differential Signaling I/O Standards | — | — | 330 | — | — | 330 | — | — | 330 | ps | |
Receiver121 | True Differential Signaling I/O Standards - fHSDRDPA (data rate) | SERDES factor J = 4 and 8115 116 117 | 600 | — | 1250122 | 600 | — | 1250122 | 600 | — | 1000122 | Mbps |
SLVS400 I/O Standards - fHSDRDPA (data rate) | SERDES factor J = 4 and 8115 116 117 | 600 | — | 891 | 600 | — | 891 | 600 | — | 891 | Mbps | |
fHSDR (data rate) (without DPA)114 | SERDES factor J = 4 and 8115 116 117 | 117 | — | 123 | 117 | — | 123 | 117 | — | 123 | Mbps | |
SERDES factor J = 2, uses DDR registers | 117 | — | 118 | 117 | — | 118 | 117 | — | 118 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 117 | — | 118 | 117 | — | 118 | 117 | — | 118 | Mbps | ||
DPA (FIFO mode) | DPA run length | — | — | — | ≤10,000 | — | — | ≤10,000 | — | — | ≤10,000 | UI |
DPA (soft CDR mode) | DPA run length | SGMII/GbE protocol | — | — | 5 | — | — | 5 | — | — | 5 | UI |
All other protocols | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | ||
Soft CDR mode | Soft-CDR ppm tolerance | — | –300 | — | 300 | –300 | — | 300 | –300 | — | 300 | ppm |
Non DPA mode | Sampling window | — | — | — | 330 | — | — | 330 | — | — | 330 | ps |