Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

HPS NAND Timing Characteristics

Table 100.  HPS NAND SDR Timing Requirements

Compatible with the ONFI 1.x and 2.x specifications. Compatible with the Toggle 1.x and 2.x specifications. HPS I/O supports SDR, NV-DDR protocols up to 200 MT/s.

For specification status, see the Data Sheet Status table

Symbol Description Min Max Unit
TWP 164 Write enable pulse width 10 ns
TWH 164 Write enable hold time 7 ns
TRP 164 Read enable pulse width 10 ns
TREH 164 Read enable hold time 7 ns
TCLS 164 Command latch enable to write enable setup time 10 ns
TCLH 164 Command latch enable to write enable hold time 5 ns
TCS 164 Chip enable to write enable setup time 15 ns
TCH 164 Chip enable to write enable hold time 5 ns
TALS 164 Address latch enable to write enable setup time 10 ns
TALH 164 Address latch enable to write enable hold time 5 ns
TDS 164 Data to write enable setup time 7 ns
TDH 164 Data to write enable hold time 5 ns
TWB 164 Write enable high to R/B low 200 ns
TCEA Chip enable to data access time 100 ns
TREA Read enable to data access time 40 ns
TRHZ Read enable to data high impedance 200 ns
TRR Ready to read enable low 20 ns
Figure 31. NAND SDR Command Latch Timing Diagram
Figure 32. NAND SDR Address Latch Timing Diagram
Figure 33. NAND SDR Data Output Cycle Timing Diagram
Figure 34. NAND SDR Data Input Cycle Timing Diagram
Figure 35. NAND SDR Data Input Timing Diagram for Extended Data Output (EDO) Cycle
Figure 36. NAND SDR Read Status Timing Diagram
Figure 37. NAND SDR Read Status Enhanced Timing Diagram
Table 101.  HPS NAND DDR Timing Requirements

Compatible with the ONFI 1.x and 2.x specifications. Compatible with the Toggle 1.x and 2.x specifications. HPS I/O supports SDR, NV-DDR protocols up to 200 MT/s.

For specification status, see the Data Sheet Status table

Symbol Description 100 MHz (200 MT/s)
Min Max Unit
tAC Access window of DQ[7:0] from CLK 3 25 ns
tADL Address cycle to data loading time 400 ns
tCADf Command, address, data delay (fast) (command to command, address to address, command to address, address to command, command/address to start of data) 25 ns
tCADs Command, address, data delay (slow) (command to command, address to address, command to address, address to command, command/address to start of data) 45 ns
tCAH Command/address DQ hold time 2 ns
tCALH W/R_n, CLE, and ALE hold time 2 ns
tCALS W/R_n, CLE, and ALE setup time 2 ns
tCAS Command/address DQ setup time 2 ns
tCEH CE_n high hold time 20 ns
tCH CE_n hold time 2 ns
tCK(avg) or tCK 165 Average clock cycle time 10 ns
tCK(abs) Absolute clock period, measured from rising edge to the next consecutive rising edge tCK(avg) + tJIT(per) min tCK(avg) + tJIT(per) max ns
tCKH(abs) 166 Clock cycle high 0.43 0.57 tCK
tCKL(abs) 166 Clock cycle low 0.43 0.57 tCK
tCKWR Data output end to W/R_n high RoundUp{[tDQSCK(max) + tCK] / tCK} tCK
tCS3 CE_n setup time for data input and data output after CE_n has been high for greater than 1 µs 75 ns
tCS CE_n setup time 15 ns
tDH Data hold time 0.9 ns
tDPZ Data input pause setup time 1.5 tDSC
tDQSCK Access window of DQS from CLK 3 25 ns
tDQSD W/R_n low to DQS/DQ driven by device 0 18 ns
tDQSH 167 DQS input high pulse width 0.4 0.6 tCK or tDSC4
tDQSHZ 168 W/R_n high to DQS/DQ tri-state by device 20 ns
tDQSL 167 DQS input low pulse width 0.4 0.6 tCK or tDSC4
tDQSQ DQS-DQ skew, DQS to last DQ valid, per access 0.85 ns
tDQSS Data input to first DQS latching transition 0.75 1.25 tCK
tDS Data setup time 0.9 ns
tDSC DQS cycle time 10 ns
tDSH DQS falling edge to CLK rising – hold time 0.2 tCK
tDSS DQS falling edge to CLK rising – setup time 0.2 tCK
tDVW Output data valid window tDVW = tQH – tDQSQ ns
tFEAT Busy time for Set Features and Get Features 1 µs
tHP Half-clock period tHP = min(tCKL, tCKH) ns
tITC Interface and Timing Mode Change time 1 µs
tJIT(per) The deviation of a given tCK(abs) from tCK(avg) –0.5 0.5 ns
tQH DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH = tHP – tQHS ns
tQHS Data hold skew factor 1 ns
tRHW Data output cycle to command, address, or data input cycle 100 ns
tRR Ready to data output cycle (data only) 20 ns
tRST (raw NAND) Device reset time, measured from the falling edge of R/B_n to the rising edge of R/B_n 15/30/500 µs
tRST (EZ NAND)169 Device reset time, measured from the falling edge of R/B_n to the rising edge of R/B_n 150/150/500 µs
tWB (WE_n high or CLK rising edge) to SR[6] low 100 ns
tWHR Command, address, or data input cycle to data output cycle 80 ns
tWPRE DQS write preamble 1.5 tCK
tWPST DQS write postamble 1.5 tCK
tWRCK W/R_n low to data output cycle 20 ns
tWW WP_n transition to command cycle 100 ns
Figure 38. NAND DDR Command Cycle Timing Diagram
Figure 39. NAND DDR Address Cycle Timing Diagram
Figure 40. NAND DDR Data Input Cycle Timing Diagram
Figure 41. NAND DDR Data Input Cycle Timing Diagram (CLK Stopped)
Figure 42. NAND DDR Data Input Cycle Timing Diagram (CLK Stopped with Data Pause)
Figure 43. NAND DDR Data Output Cycle Timing Diagram
Figure 44. NAND DDR W/R_n Timing Diagram
Figure 45. NAND DDR Read Status Including tWHR and tCAD Timing Diagram
164 This timing is software programmable. Refer to the NAND Flash Controller chapter in the Hard Processor System Technical Reference Manual for more information about software-programmable timing in the NAND flash controller.
165 tCK(avg) is the average clock period over any consecutive 200 cycles window.
166 tCKH(abs) and tCKL(abs) include static offset and duty cycle jitter.
167 tDQSL and tDQSH are relative to tCK when CLK is running. If CLK is stopped during data input, then tDQSL and tDQSH are relative to tDSC.
168 tDQSHZ is not referenced to a specific voltage level, but specifies when the device output is no longer driving.
169 If the reset is invoked using a Reset (FFh) command then the EZ NAND device has 250 ms to complete the reset operation regardless of the timing mode. If the reset is invoked using Synchronous Reset (FCh) or a Reset LUN (FAh) command then the values are as shown.