Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

I/O PLL Specifications

Table 47.  D-Series FPGAs I/O PLL Specifications For specification status, see the Data Sheet Status table
Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency source from core clock input and reference clock input –1V 10 1,10078 MHz
–2V 10 1,00078 MHz
–3V 10 78078 MHz
Input clock frequency source from I/O clock input –1V 10 80078 MHz
–2V 10 71778 MHz
–3V 10 62578 MHz
fINPFD Input clock frequency to the PFD 10 325 MHz
fVCO I/O PLL VCO operating range –1V 600 3,200 MHz
–2V 600 3,200 MHz
–3V 600 2,400 MHz
fCLBW I/O PLL closed-loop bandwidth 0.5 20 MHz
fOUT Output frequency for internal clock (C counter) –1V 1,100 MHz
–2V 1,000 MHz
–3V 780 MHz
fOUT_EXT Output frequency for external clock output –1V 800 MHz
–2V 717 MHz
–3V 625 MHz
tOUTDUTY Duty cycle for dedicated external clock output (when set to 50%) fOUT_EXT < 300 MHz 45 50 55 %
fOUT_EXT ≥ 300 MHz 40/45 79 50 55 79/60 %
tFCOMP 80 External feedback clock compensation time 5 ns
fDYCONFIGCLK Dynamic configuration clock for mgmt_clk 100 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of areset 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) 1 ms
tPLL_PSERR 81 Accuracy of PLL phase shift ±50 ps
tARESET Minimum pulse width on the areset signal 10 ns
tINCCJ Input clock cycle-to-cycle jitter fREF < 100 MHz 82 ±750 ps (p-p)
fREF ≥ 100 MHz 82 0.15 UI (p-p)
tREFPJ Reference phase jitter (rms)83 Carrier frequency: 100 MHz with integrated bandwidth of 10 kHz to 50 MHz 1.42 ps
tREFPN Reference phase noise84 83 10 Hz –90 dBc/Hz
100 Hz –100 dBc/Hz
1 kHz –110 dBc/Hz
10 kHz –120 dBc/Hz
100 kHz –130 dBc/Hz
1 MHz –138 dBc/Hz
10 MHz –142 dBc/Hz
100 MHz –144 dBc/Hz
tOUTPJ_DC 80 85 Period jitter for dedicated clock output fOUT < 100 MHz 82 17.5 mUI (p-p)
fOUT ≥ 100 MHz 82 175 ps (p-p)
tOUTCCJ_DC 80 85 Cycle-to-cycle jitter for dedicated clock output fOUT < 100 MHz 82 17.5 mUI (p-p)
fOUT ≥ 100 MHz 82 175 ps (p-p)
tOUTPJ_IO 86 85 Period jitter for clock output on the regular I/O fOUT < 100 MHz 82 60 mUI (p-p)
fOUT ≥ 100 MHz 82 600 ps (p-p)
tOUTCCJ_IO 86 85 Cycle-to-cycle jitter for clock output on the regular I/O fOUT < 100 MHz 82 60 mUI (p-p)
fOUT ≥ 100 MHz 82 600 ps (p-p)
tCASC_OUTPJ_DC 80 Period jitter for dedicated clock output in cascaded PLLs fOUT < 100 MHz 82 17.5 mUI (p-p)
fOUT ≥ 100 MHz 82 175 ps (p-p)
Table 48.  E-Series FPGAs I/O PLL Specifications For specification status, see the Data Sheet Status table
Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency source from core clock input and reference clock input –1V, –4S 10 1,10087 MHz
–2V, –2E, –5S 10 1,00087 MHz
–3V, –6S, –6X 10 78087 MHz
Input clock frequency source from I/O clock input –1V, –4S 10 80087 MHz
–2V, –2E, –5S 10 71787 MHz
–3V, –6S, –6X 10 62587 MHz
fINPFD Input clock frequency to the PFD 10 325 MHz
fVCO I/O PLL VCO operating range –1V, –4S 600 3,200 MHz
–2V, –2E, –5S 600 3,200 MHz
–3V, –6S, –6X 600 2,400 MHz
fCLBW I/O PLL closed-loop bandwidth 0.5 20 MHz
fOUT Output frequency for internal clock (C counter) –1V,–4S 1,100 MHz
–2V, –2E, –5S 1,000 MHz
–3V, –6S, –6X 780 MHz
fOUT_EXT Output frequency for external clock output –1V, –4S 800 MHz
–2V, –2E, –5S 717 MHz
–3V, –6S, –6X 625 MHz
tOUTDUTY Duty cycle for dedicated external clock output (when set to 50%) fOUT_EXT < 300 MHz 45 50 55 %
fOUT_EXT ≥ 300 MHz 40/45 88 50 55 88/60 %
tFCOMP 89 External feedback clock compensation time 5 ns
fDYCONFIGCLK Dynamic configuration clock for mgmt_clk 100 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of areset 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) 1 ms
tPLL_PSERR 90 Accuracy of PLL phase shift ±50 ps
tARESET Minimum pulse width on the areset signal 10 ns
tINCCJ Input clock cycle-to-cycle jitter fREF < 100 MHz 91 ±750 ps (p-p)
fREF ≥ 100 MHz 91 0.15 UI (p-p)
tREFPJ Reference phase jitter (rms)92 Carrier frequency: 100 MHz with integrated bandwidth of 10 kHz to 50 MHz 1.42 ps
tREFPN Reference phase noise93 92 10 Hz –90 dBc/Hz
100 Hz –100 dBc/Hz
1 kHz –110 dBc/Hz
10 kHz –120 dBc/Hz
100 kHz –130 dBc/Hz
1 MHz –138 dBc/Hz
10 MHz –142 dBc/Hz
100 MHz –144 dBc/Hz
tOUTPJ_DC 89 94 Period jitter for dedicated clock output fOUT < 100 MHz 91 17.5 mUI (p-p)
fOUT ≥ 100 MHz 91 175 ps (p-p)
tOUTCCJ_DC 89 94 Cycle-to-cycle jitter for dedicated clock output fOUT < 100 MHz 91 17.5 mUI (p-p)
fOUT ≥ 100 MHz 91 175 ps (p-p)
tOUTPJ_IO 95 94 Period jitter for clock output on the regular I/O fOUT < 100 MHz 91 60 mUI (p-p)
fOUT ≥ 100 MHz 91 600 ps (p-p)
tOUTCCJ_IO 95 94 Cycle-to-cycle jitter for clock output on the regular I/O fOUT < 100 MHz 91 60 mUI (p-p)
fOUT ≥ 100 MHz 91 600 ps (p-p)
tCASC_OUTPJ_DC 89 Period jitter for dedicated clock output in cascaded PLLs fOUT < 100 MHz 91 17.5 mUI (p-p)
fOUT ≥ 100 MHz 91 175 ps (p-p)
78 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
79 To achieve 5% duty cycle for fOUT_EXT ≥ 300 MHz, you only can use tx_outclk port from the LVDS SERDES Intel FPGA IP. Refer to the Clocking and PLL User Guide for the detail design guidelines.
80 Not applicable for fabric-feeding I/O PLL.
81 PLL phase shift accuracy is 50 ps with the assumption of fVCO = 1.6 GHz.
82 fREF is fIN/N, specification applies when N = 1.
83 Requirement for DDR/LPDDR protocol and LVDS SERDES applications only.
84 The phase noise numbers in this table are the maximum acceptable phase noise values measured at a carrier frequency of 100 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 100 MHz + (20 × log10 (f/100)).
85 This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend on the spread-spectrum clock profile used. Refer to the Clocking and PLL User Guide for the recommended spread-spectrum clock profile.
86 External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory Output clock Jitter Specifications table.
87 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
88 To achieve 5% duty cycle for fOUT_EXT ≥ 300 MHz, you only can use tx_outclk port from the LVDS SERDES Intel FPGA IP. Refer to the Clocking and PLL User Guide for the detail design guidelines.
89 Not applicable for fabric-feeding I/O PLL.
90 PLL phase shift accuracy is 50 ps with the assumption of fVCO = 1.6 GHz.
91 fREF is fIN/N, specification applies when N = 1.
92 Requirement for DDR/LPDDR protocol and LVDS SERDES applications only.
93 The phase noise numbers in this table are the maximum acceptable phase noise values measured at a carrier frequency of 100 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 100 MHz + (20 × log10 (f/100)).
94 This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend on the spread-spectrum clock profile used. Refer to the Clocking and PLL User Guide for the recommended spread-spectrum clock profile.
95 External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory Output clock Jitter Specifications table.