Agilex™ 5 FPGAs and SoCs Device Data Sheet

ID 813918
Date 8/05/2024
Public
Document Table of Contents

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, the toggling input data or clock signals may overshoot to the voltage listed in the following tables and undershoot to the following limits for input currents less than 100 mA and periods shorter than 20 ns.
  • Undershoot limit of –1.1 V when using VCCIO_HPS or VCCIO_SDM of 1.8 V.
  • Undershoot limit of –0.3 V when using VCCIO_PIO of 1.3 V, 1.2 V, 1.1 V, 1.05 V, and 1.0 V.

No overshooting beyond 1.602 V and undershooting below 0.273 V is allowed when using True Differential Signaling I/O standard at VCCIO_PIO = 1.3 V.

No overshooting beyond 1.177 V and undershooting below 0.573 V is allowed when using True Differential Signaling I/O standard at VCCIO_PIO = 1.2 V, 1.1 V, and 1.05 V.

The maximum allowed overshoot duration is specified as a percentage of high time (calculated as ([delta T]/T) × 100) over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

Table 5.  Maximum Allowed Overshoot During Transitions for 1.0 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %
VCCIO_PIO + 0.3021 30 %
VCCIO_PIO + 0.35 4 %
> VCCIO_PIO + 0.40 No overshoot allowed %
Table 6.  Maximum Allowed Overshoot During Transitions for 1.05 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %
VCCIO_PIO + 0.3022 30 %
VCCIO_PIO + 0.35 4 %
> VCCIO_PIO + 0.40 No overshoot allowed %
Table 7.  Maximum Allowed Overshoot During Transitions for 1.1 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %
VCCIO_PIO + 0.3023 30 %
VCCIO_PIO + 0.35 4 %
> VCCIO_PIO + 0.40 No overshoot allowed %
Table 8.  Maximum Allowed Overshoot During Transitions for 1.2 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %
VCCIO_PIO + 0.3024 30 %
VCCIO_PIO + 0.35 4 %
> VCCIO_PIO + 0.40 No overshoot allowed %
Table 9.  Maximum Allowed Overshoot During Transitions for 1.3 V I/O in HSIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %
VCCIO_PIO + 0.3025 65 %
VCCIO_PIO + 0.35 7 %
> VCCIO_PIO + 0.40 No overshoot allowed %
Table 10.  Maximum Allowed Overshoot During Transitions for 1.8 V I/O in HPS and SDM I/O Banks

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_SDM + 0.30, VCCIO_HPS + 0.30 100 %
VCCIO_SDM + 0.35, VCCIO_HPS + 0.35 60 %
VCCIO_SDM + 0.40, VCCIO_HPS + 0.40 30 %
VCCIO_SDM + 0.45, VCCIO_HPS + 0.45 20 %
VCCIO_SDM + 0.50, VCCIO_HPS + 0.50 10 %
VCCIO_SDM + 0.55, VCCIO_HPS + 0.55 6 %
> VCCIO_SDM + 0.55, > VCCIO_HPS + 0.55 No overshoot allowed %
Table 11.  Maximum Allowed Overshoot During Transitions for 1.8 V, 2.5 V, and 3.3 V in HVIO Bank

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_HVIO + 0.30 100 %
VCCIO_HVIO + 0.35 42 %
VCCIO_HVIO + 0.40 18 %
VCCIO_HVIO + 0.45 9 %
VCCIO_HVIO + 0.50 4 %
> VCCIO_HVIO + 0.55 No overshoot allow %

For example, when using 1.2 V I/O standard with 1.26 V VCCIO_PIO, a signal that overshoots to 1.61 V can only be at 1.61 V for ~4% over the lifetime of the device. For an overshoot of 1.51 V, the percentage of high time for the overshoot can be as high as 100% over the lifetime of the device.

Figure 1. Overshoot Duration Example (for 1.2 V HSIO Bank at VCCIO_PIO = 1.26 V)
21 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V at an overshoot duration of 100%.
22 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V at an overshoot duration of 100%.
23 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V at an overshoot duration of 100%.
24 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V at an overshoot duration of 100%.
25 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V at an overshoot duration of 100%.