Visible to Intel only — GUID: ocb1662081155564
Ixiasoft
HSIO Single-Ended I/O Standards Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
HSIO Single-Ended LVSTL I/O Standards Specifications
HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications
HSIO Differential POD I/O Standards Specifications
HSIO Differential LVSTL I/O Standards Specifications
HSIO Differential I/O Standards Specifications
MIPI D-PHY I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/eMMC Timing Characteristics
HPS USB 2.0 Timing Characteristics
HPS USB 3.1 Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS I3C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: ocb1662081155564
Ixiasoft
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
I/O Standard | VCCIO_PIO (V) | Internal VREF (V) | VTT (V) | ||||||
---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | |
SSTL-12 | 1.14 | 1.2 | 1.26 | 0.49 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.51 × VCCIO_PIO | 0.45 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.55 × VCCIO_PIO |
HSTL-12 | 1.14 | 1.2 | 1.26 | 0.47 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.53 × VCCIO_PIO | 0.45 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.55 × VCCIO_PIO |
HSUL-1264 | 1.14 | 1.2 | 1.26 | 0.49 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.51 × VCCIO_PIO | 0.45 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.55 × VCCIO_PIO |
POD1265 | 1.164 | 1.2 | 1.236 | 0.69 × VCCIO_PIO | 0.7 × VCCIO_PIO | 0.71 × VCCIO_PIO | — | VCCIO_PIO | — |
POD1165 | 1.067 | 1.1 | 1.133 | 0.69 × VCCIO_PIO | 0.7 × VCCIO_PIO | 0.71 × VCCIO_PIO | — | VCCIO_PIO | — |
LVSTL1165 | 1.067 | 1.1 | 1.133 | 0.075 | 0.2 | 0.35 | — | GND | — |
LVSTL10565 | 1.0185 | 1.05 | 1.0815 | 0.075 | 0.2 | 0.35 | — | GND | — |
LVSTL700 | 1.0185 | 1.05 | 1.0815 | 0.075 | 0.2 | 0.35 | — | GND | — |
64 Usage of receiver termination is optional.
65 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-bank is operating in any of the following modes. Else, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.
- PHYLITE mode
- GPIO mode