Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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6.1.2.1. System Interconnect Firewalls

You can use the system interconnect firewalls to enforce security policies for slave and memory regions in the system interconnect. The firewalls support the following features:

  • For each peripheral, can implement secure or non-secure access.
  • Allows configuration of individual transactions as secure or non-secure at the initiating master.
  • For certain peripherals, can implement two levels of access: privileged or user.

You can program the security configuration registers (SCRs) to set security policies and define which transactions the firewall allows. Transactions that the firewall blocks result in a bus error.

The HPS has the following firewalls:

  • Peripheral
  • System
  • HPS-to-FPGA
  • Lightweight HPS-to-FPGA
  • Debug access port
  • TCU