Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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16.5.5.4. Single-Block or Multiple-Block Read

To implement a single‑block or multiple‑block read, the software performs the following steps:
  1. Write the data size in bytes to the bytcnt register. For a multi‑block read, bytcnt must be a multiple of the block size.
  2. Write the block size in bytes to the blksiz register. The controller expects data to return from the card in blocks of size blksiz.
  3. If the read round trip delay, including the card delay, is greater than half of sdmmc_clk_divided, write to the card threshold control register (cardthrctl) to ensure that the card clock does not stop in the middle of a block of data being transferred from the card to the host. For more information, refer to Card Read Threshold.
    Note: If the card read threshold enable bit (cardrdthren) is 0, the host system must ensure that the RX FIFO buffer does not become full during a read data transfer by ensuring that the RX FIFO buffer is read at a rate faster than that at which data is written into the FIFO buffer. Otherwise, an overflow might occur.
  4. Write the cmdarg register with the beginning data address for the data read.
  5. Write the cmd register with the parameters listed in cmd Register Settings for Single-Block and Multiple-Block Reads. For SD and MMC cards, use the SD/SDIO READ_SINGLE_BLOCK (CMD17) command for a single‑block read and the READ_MULTIPLE_BLOCK (CMD18) command for a multiple‑block read. For SDIO cards, use the IO_RW_EXTENDED (CMD53) command for both single‑block and multiple‑block transfers. The command argument for (CMD53) is shown in the figure, below. After writing to the cmd register, the controller starts executing the command. When the command is sent to the bus, the Command Done interrupt is generated.
  6. Software must check for data error interrupts, reported in the dcrc, bds, sbe, and ebe bits of the rintsts register. If required, software can terminate the data transfer by sending an SD/SDIO STOP command.
  7. Software must check for host timeout conditions in the rintsts register:
    • Receive FIFO buffer data request
    • Data starvation from host—the host is not reading from the FIFO buffer fast enough to keep up with data from the card. To correct this condition, software must perform the following steps:
      • Read the fifo_count field of the status register
      • Read the corresponding amount of data out of the FIFO buffer

    In both cases, the software must read data from the FIFO buffer and make space in the FIFO buffer for receiving more data.

  8. When a DTO interrupt is received, the software must read the remaining data from the FIFO buffer.
Figure 57. Command Argument for IO_RW_EXTENDED (CMD53)