Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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Document Table of Contents

17.6.3.2.1. Receive Descriptor Field 0 (RDES0)

Table 176.  Receive Descriptor Field 0 (RDES0)

Bit

Description

31

OWN: Own Bit

When set, this bit indicates that the descriptor is owned by the DMA of the EMAC. When this bit is cleared, this bit indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes the frame reception or when the buffers that are associated with this descriptor are full.

30

AFM: Destination Address Filter Fail

When set, this bit indicates a frame that failed in the DA Filter in the MAC. 

29:16

FL: Frame Length

These bits indicate the byte length of the received frame that was transferred to host memory (including CRC). This field is valid when Last Descriptor (RDES0[8]) is set and either the Descriptor Error (RDES0[14]) or Overflow Error bits are cleared. The frame length also includes the two bytes appended to the Ethernet frame when IP checksum calculation (Type 1) is enabled and the received frame is not a MAC control frame.

This field is valid when Last Descriptor (RDES0[8]) is set. When the Last Descriptor and Error Summary bits are not set, this field indicates the accumulated number of bytes that have been transferred for the current frame. 

15

ES: Error Summary

Indicates the logical OR of the following bits:

  • RDES0[1]: CRC Error
  • RDES0[3]: Receive Error
  • RDES0[4]: Watchdog Timeout
  • RDES0[6]: Late Collision
  • RDES0[7]: Giant Frame
  • RDES4[4:3]: IP Header or Payload Error (Receive Descriptor Field 4 (RDES4))
  • RDES0[11]: Overflow Error
  • RDES0[14]: Descriptor Error

This field is valid only when the Last Descriptor (RDES0[8]) is set. 

14

DE: Descriptor Error

When set, this bit indicates a frame truncation caused by a frame that does not fit within the current descriptor buffers, and that the DMA does not own the Next descriptor. The frame is truncated. This bit is valid only when the Last Descriptor (RDES0[8]) bit is set. 

13

SAF: Source Address Filter Fail

When set, this bit indicates that the SA field of frame failed the SA Filter in the MAC. 

12

LE: Length Error

When set, this bit indicates that the actual length of the frame received and that the Length/ Type field does not match. This bit is valid only when the Frame Type (RDES0[5]) bit is clear. 

11

OE: Overflow Error

When set, this bit indicates that the received frame was damaged because of buffer overflow in MTL.

Note: This bit is set only when the DMA transfers a partial frame to the application, which happens only when the RX FIFO buffer is operating in the threshold mode. In the store‑and‑forward mode, all partial frames are dropped completely in the RX FIFO buffer. 

10

VLAN: VLAN Tag

When set, this bit indicates that the frame to which this descriptor is pointing is a VLAN frame tagged by the MAC. The VLAN tagging depends on checking the VLAN fields of the received frame based on the Register 7 (VLAN Tag Register) setting. 

9

FS: First Descriptor

When set, this bit indicates that this descriptor contains the first buffer of the frame. If the size of the first buffer is 0, the second buffer contains the beginning of the frame. If the size of the second buffer is also 0, the next descriptor contains the beginning of the frame. 

8

LD: Last Descriptor

When set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of the frame. 

7

Timestamp Available

When set, bit[7] indicates that a snapshot of the Timestamp is written in descriptor words 6 (RDES6) and 7 (RDES7). This is valid only when the Last Descriptor bit (RDES0[8]) is set.

6

LC: Late Collision

When set, this bit indicates that a late collision has occurred while receiving the frame in the half‑duplex mode. 

5

FT: Frame Type

When set, this bit indicates that the receive frame is an Ethernet‑type frame (the LT field is greater than or equal to 0x0600). When this bit is cleared, it indicates that the received frame is an IEEE802.3 frame. This bit is not valid for Runt frames less than 14 bytes.

4

RWT: Receive Watchdog Timeout

When set, this bit indicates that the receive Watchdog Timer has expired while receiving the current frame and the current frame is truncated after the Watchdog Timeout. 

3

RE: Receive Error

When set, this bit indicates that the gmii_rxer_i signal is asserted while gmii_rxdv_i is asserted during frame reception.

2

DE: Dribble Bit Error

When set, this bit indicates that the received frame has a non‑integer multiple of bytes (odd nibbles). This bit is valid only in the MII Mode. 

1

CE: CRC Error

When set, this bit indicates that a CRC error occurred on the received frame. This bit is valid only when the Last Descriptor (RDES0[8]) is set. 

0

Extended Status Available/RX MAC Address

When either advanced timestamp or IP Checksum Offload (Type 2) is present, this bit, when set, indicates that the extended status is available in descriptor word 4 (RDES4). This bit is valid only when the Last Descriptor bit (RDES0[8]) is set.

When the Advance Timestamp Feature or IPC Full Offload is not selected, this bit indicates RX MAC Address status. When set, this bit indicates that the RX MAC Address registers value (1 to 15) matched the frame’s DA field. When clear, this bit indicates that the RX MAC Address Register 0 value matched the DA field.