Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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Document Table of Contents

3.5.4.1. Instruction Cache

The instruction cache is 2-way set associative. The instruction cache provides parity checking to detect single-bit errors. If an error is detected, the line is invalidated and fetched again. The instruction cache is designed to reduce instruction fetching latency by implementing prefetch and branch prediction logic.
  • Instruction fetches are sequential
  • A two-instruction transparent target instruction cache and 256-entry branch target address cache provides reduced branch latency
  • An 8-entry return stack accelerates branch returns
  • The read interface to the 1 MB L2 cache is 128-bits wide

A cache line is 64 bytes and only holds one instruction type. Different instruction types cannot be mixed in the same cache line.

Each cache line can hold the following:

  • 16—A32 instructions
  • 16—32-bit T32 instructions
  • 16—A64 instructions
  • 32—16-bit T32 instructions

The instruction cache supports single error detection (SED) parity checking.