Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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Document Table of Contents

16.4.3.4.2. Data Transmit†

  • No CRC status—during a write data transfer, if the CRC status start bit is not received for two clock cycles after the end bit of the data block is sent out, the data path performs the following actions:
    • Signals no CRC status error to the BIU
    • Terminates further data transfer
    • Signals data transfer done to the BIU
  • Negative CRC—if the CRC status received after the write data block is negative (that is, not 0b010), the data path signals a data CRC error to the BIU and continues with the data transfer.
  • Data starvation due to empty FIFO buffer—if the FIFO buffer becomes empty during a write data transmission, or if the card clock stopped and the FIFO buffer remains empty for a data-timeout number of clock cycles, the data path signals a data‑starvation error to the BIU and the data path continues to wait for data in the FIFO buffer.