Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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7.4.1. HPS-to-FPGA Bridge Signals

All the HPS-to-FPGA bridge master signals have a fixed width except the data and write strobes for the read and write data channels. The variable-width signals depend on the data width setting of the bridge interface exposed to the FPGA logic.

The HPS-to-FPGA bridge incorporates the ARM® TrustZone* technology by providing the ARPROT[1] and AWPROT[1] signals, which specify whether a transaction is secure or non-secure. The firewalls use these signals to determine whether each bus access is valid.

All peripheral slaves and memories in the SoC are secure when they are released from reset.

The following table lists signals exposed by the HPS-to-FPGA master interface to the FPGA fabric.

Table 79.   HPS-to-FPGA Bridge Signals
Name Direction Description
h2f_axi_clock Input Clock source from FPGA.
h2f_axi_reset Input Module reset signal from Reset Manager.
soc2fpga_port_size_config[1:0] Input Port width configuration signal from FPGA:
  • 00: 32-bit
  • 01: 64-bit
  • 10: 128-bit
  • 11: Reserved
Table 80.   HPS-to-FPGA Bridge Master Write Address Channel Signals
Signal Width Direction Description
AWID

4 bits

Output

Write address ID

AWADDR

32 bits

Output

Write address

AWLEN

8 bits

Output

Burst length

AWSIZE

3 bits

Output

Burst size