Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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7.1. Features of the Bridges

The bridges allow masters in the FPGA fabric to communicate with slaves in the HPS logic and vice versa. For example, you can instantiate additional memories or peripherals in the FPGA fabric, and master interfaces belonging to components in the HPS logic can access them. You can also instantiate components such as a Nios® II processor in the FPGA fabric and their master interfaces can access memories or peripherals in the HPS logic FPGA-to-HPS.
Table 65.   Bridge Features

Feature

FPGA-to-HPS

HPS-to-FPGA

Lightweight HPS-to-FPGA

Interface support

ACE Lite AMBA AXI4 AMBA AXI4

Implements clock crossing and manages the transfer of data across the clock domains in the HPS logic and the FPGA fabric

Y Y Y

Performs data width conversion between the HPS logic and the FPGA fabric

Y Y Y

Allows configuration of FPGA interface widths at instantiation time

Y Y N

Each bridge consists of a master-slave pair with one interface exposed to the FPGA fabric and the other exposed to the HPS logic.