Intel® Agilex™ Hard Processor System Technical Reference Manual

ID 683567
Date 2/14/2023
Public

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14.1. Features of the Intel® Agilex™ HPS I/O Block

The I/O block provides the following functionality and features:

  • Dedicated HPS I/O pins
    • 48 pins available for HPS clock, external flash memories and peripherals.
    Note: The HPS also interfaces with an SDRAM memory controller. This interface is separate from the dedicated pins discussed in this chapter.
  • I/O multiplexing
    • Selects pins used by each HPS peripheral
    • Can expose HPS peripheral interfaces to FPGA logic
      Note: When routed to the FPGA, some HPS peripherals require additional pipeline support in the connected soft logic. Refer to the relevant HPS peripheral chapter for details.

    You configure I/O multiplexing when you instantiate the HPS component in Platform Designer.